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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-02-08 22:14:17 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-09 21:16:10 +0000 |
| commit | aecca7592b65f68bb45075e3f13af97676463ef6 (patch) | |
| tree | 51e0e71b731487e38b758e4e6cddf8f0ddc57f33 | |
| parent | 060b8ad7a324d8aada887133fd1222a9d66c678b (diff) | |
soc/amd/stoneyridge/cpu: use MSR_PSP_ADDR define instead of hex number
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id9042def0f5e9d2fa994d6729c592c7e2152976b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
| -rw-r--r-- | src/soc/amd/stoneyridge/cpu.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index c898ff7f93..9992fc54aa 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -16,6 +16,7 @@ #include <soc/smi.h> #include <soc/iomap.h> #include <console/console.h> +#include <amdblocks/psp.h> /* * MP and SMM loading initialization. @@ -121,10 +122,10 @@ static void model_15_init(struct device *dev) uint32_t psp_bar; /* Note: NDA BKDG names this 32-bit register BAR3 */ psp_bar = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4); psp_bar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; - psp_msr = rdmsr(0xc00110a2); + psp_msr = rdmsr(MSR_PSP_ADDR); if (psp_msr.lo == 0) { psp_msr.lo = psp_bar; - wrmsr(0xc00110a2, psp_msr); + wrmsr(MSR_PSP_ADDR, psp_msr); } } |