diff options
| author | Frank Chu <frank_chu@pegatron.corp-partner.google.com> | 2020-11-19 15:13:45 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-30 08:07:50 +0000 |
| commit | ae99ea5f08ffa3f59864c5ed7f06e00db31218fd (patch) | |
| tree | dbe37038c06cf513e5e0981d01a53314e73e5f43 | |
| parent | 092813a50ce4198d622daa809181216b6ffd1bd4 (diff) | |
mb/google/volteer/variants/delbin: Enhance I2C5 bus freq closer 400 kHz
The current I2C5 bus frequency is 367 kHZ, which does not meet the spec.
This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring
the bus frequency closer to 400kHz.
BUG=b:173670150
TEST=Verified that I2C5 frequency is between 386-387kHz.
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I6d60abe15645dc51ed9ee30975d2521b8940c2d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47736
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/volteer/variants/delbin/overridetree.cb | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index bd4bf8041e..904f3e0e2e 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -2,6 +2,49 @@ chip soc/intel/tigerlake register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | WLAN, SAR0 | + #| I2C3 | Camera, SAR1 | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 163, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, + }" + # Acoustic settings register "AcousticNoiseMitigation" = "1" register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" |