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authorLijian Zhao <lijian.zhao@intel.com>2018-12-12 11:19:46 -0800
committerPatrick Georgi <pgeorgi@google.com>2018-12-19 05:19:33 +0000
commitae75400ae338180da9a75526b017042a1780c4f9 (patch)
tree5470fb90ec87c86a7a1df3479229abe83e52af83
parent4e21dee863ed5622b83a6461c00c8911b608d323 (diff)
soc/intel/cannonlake: Add Acoustic features
Expose the following FSP UPD interface into coreboot, which is the following: AcousticNoiseMitigation FastPkgCRampDisableIa FastPkgCRampDisableGt FastPkgCRampDisableSa FastPkgCRampDisableFivr SlowSlewRateForIa SlowSlewRateForGt SlowSlewRateForSa SlowSlewRateForFivr Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I21f53c594a085794474e87eb6781b51db88d0c10 Reviewed-on: https://review.coreboot.org/c/30207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
-rw-r--r--src/soc/intel/cannonlake/chip.h31
-rw-r--r--src/soc/intel/cannonlake/fsp_params.c11
2 files changed, 42 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 9eb91bdac1..8eaf02b204 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -263,6 +263,37 @@ struct soc_intel_cannonlake_config {
/* Intel VT configuration */
uint8_t VtdDisable;
uint8_t VmxEnable;
+
+ /*
+ * Acoustic Noise Mitigation
+ * 0b - Disable
+ * 1b - Enable noise mitigation
+ */
+ uint8_t AcousticNoiseMitigation;
+
+ /*
+ * Disable Fast Package C-state ramping
+ * Need to set AcousticNoiseMitigation = '1' first
+ * 0b - Enabled
+ * 1b - Disabled
+ */
+ uint8_t FastPkgCRampDisableIa;
+ uint8_t FastPkgCRampDisableGt;
+ uint8_t FastPkgCRampDisableSa;
+ uint8_t FastPkgCRampDisableFivr;
+
+ /*
+ * Adjust the VR slew rates
+ * Need to set AcousticNoiseMitigation = '1' first
+ * 000b - Fast/2
+ * 001b - Fast/4
+ * 010b - Fast/8
+ * 011b - Fast/16
+ */
+ uint8_t SlowSlewRateForIa;
+ uint8_t SlowSlewRateForGt;
+ uint8_t SlowSlewRateForSa;
+ uint8_t SlowSlewRateForFivr;
};
typedef struct soc_intel_cannonlake_config config_t;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index f95745983d..a9326a41bf 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -210,6 +210,17 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
* 3 = GT unsliced, 4 = GT sliced */
for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)
fill_vr_domain_config(params, i, &config->domain_vr_config[i]);
+
+ /* Acoustic Noise Mitigation */
+ params->AcousticNoiseMitigation = config->AcousticNoiseMitigation;
+ params->SlowSlewRateForIa = config->SlowSlewRateForIa;
+ params->SlowSlewRateForGt = config->SlowSlewRateForGt;
+ params->SlowSlewRateForSa = config->SlowSlewRateForSa;
+ params->SlowSlewRateForFivr = config->SlowSlewRateForFivr;
+ params->FastPkgCRampDisableIa = config->FastPkgCRampDisableIa;
+ params->FastPkgCRampDisableGt = config->FastPkgCRampDisableGt;
+ params->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa;
+ params->FastPkgCRampDisableFivr = config->FastPkgCRampDisableFivr;
}
/* Mainboard GPIO Configuration */