ec/google/wilco: Add ACPI EC infrastructure

Add the base ACPI support for the Wilco embedded controller, using
ASL 2.0 syntax throughout.

This includes the EC device and its resources, as well as the layout
for the EC RAM and the functions needed to read and write to the EC RAM.

The EC RAM address space is typically read/write, and so the ACPI EC
device expects that a defined Field can be read and/or written.  With
this EC the read and write address spaces are different.  For example,
a read from address zero will return data that is unrelated to what a
write to address zero expects.

This makes using a typical OperationRegion to describe the EC RAM
address space somewhat impracticle, since field definitions would
overlap.  Instead, methods are provided for reading and writing to an
EC RAM offset, and the EC RAM layout is defined as a Package that
describes offset+mask for read or write fields within the EC RAM.

Change-Id: If8cfdf2633db1ccad4306fe877180ba197ee7414
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

5 files changed, 381 insertions, 0 deletions

diff --git a/src/ec/google/wilco/acpi/ec.asl b/src/ec/google/wilco/acpi/ec.asl
new file mode 100644
index 0000000000..8197c549a7
--- /dev/null
+++ b/src/ec/google/wilco/acpi/ec.asl
@@ -0,0 +1,137 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Device (EC0)
+{
+	Name (_HID, EisaId ("PNP0C09"))
+	Name (_UID, 1)
+	Name (_GPE, EC_SCI_GPI)
+	Name (_STA, 0xf)
+
+	Name (_CRS, ResourceTemplate() {
+		IO (Decode16,
+		    CONFIG_EC_BASE_ACPI_DATA,
+		    CONFIG_EC_BASE_ACPI_DATA,
+		    4, 4)
+		IO (Decode16,
+		    CONFIG_EC_BASE_ACPI_COMMAND,
+		    CONFIG_EC_BASE_ACPI_COMMAND,
+		    4, 4)
+	})
+
+	/* Handle registration of EmbeddedControl region */
+	Name (EREG, Zero)
+	OperationRegion (ERAM, EmbeddedControl, 0, 0xff)
+	Method (_REG, 2)
+	{
+		/* Indicate region is registered */
+		EREG = Arg1
+
+		/* Store initial value for power status */
+		ECPR = R (APWR)
+
+		/* Indicate to EC that OS is ready for queries */
+		W (ERDY, One)
+
+		/* Tell EC to stop emulating PS/2 mouse */
+		W (PS2M, Zero)
+	}
+
+	/*
+	 * Find bitmask for field
+	 *  Arg0 = EC field structure
+	 *  Arg1 = Value
+	 */
+	Method (EBIT, 2, NotSerialized)
+	{
+		Local0 = DeRefOf (Arg0[1])	/* Mask */
+		Local1 = Arg1 & Local0
+		FindSetRightBit (Local0, Local2)
+		If (Local2) {
+			Local1 >>= Local2 - 1
+		}
+		Return (Local1)
+	}
+
+	/*
+	 * READ or WRITE from EC region
+	 *  Arg0 = EC field structure
+	 *  Arg1 = Value to write
+	 */
+	Method (ECRW, 2, Serialized)
+	{
+		If (!EREG) {
+			Return (Zero)
+		}
+
+		Local0 = DeRefOf (Arg0[0])	/* Byte offset */
+		Local1 = DeRefOf (Arg0[1])	/* Mask */
+		Local2 = DeRefOf (Arg0[2])	/* Read/Write */
+
+		OperationRegion (ERAM, EmbeddedControl, Local0, 2)
+		Field (ERAM, ByteAcc, Lock, WriteAsZeros)
+		{
+			BYT1, 8,
+			BYT2, 8,
+		}
+
+		If (Local2 == RD) {
+			/* Read first byte */
+			Local3 = BYT1
+
+			/* Read second byte if needed */
+			FindSetLeftBit (Local1, Local4)
+			If (Local4 > 8) {
+				Local4 = BYT2
+				Local4 <<= 8
+				Local3 |= Local4
+			}
+
+			Local5 = EBIT (Arg0, Local3)
+			Printf ("ECRD %o = %o", Local0, Local5)
+			Return (Local5)
+		} ElseIf (Local2 == WR) {
+			/* Write byte */
+			Printf ("ECWR %o = %o", Local0, Arg1)
+			BYT1 = Arg1
+		}
+		Return (Zero)
+	}
+
+	/*
+	 * Read a field from EC
+	 *  Arg0 = EC field structure
+	 */
+	Method (R, 1, Serialized)
+	{
+		Return (ECRW (Arg0, Zero))
+	}
+
+	/*
+	 * Write value to a field from EC
+	 *  Arg0 = EC field structure
+	 *  Arg1 = Value to write
+	 */
+	Method (W, 2, Serialized)
+	{
+		Return (ECRW (Arg0, Arg1))
+	}
+
+	#include "ec_dev.asl"
+	#include "ec_ram.asl"
+	#include "lid.asl"
+	#include "platform.asl"
+}
diff --git a/src/ec/google/wilco/acpi/ec_dev.asl b/src/ec/google/wilco/acpi/ec_dev.asl
new file mode 100644
index 0000000000..0519ff0cd9
--- /dev/null
+++ b/src/ec/google/wilco/acpi/ec_dev.asl
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Device (WLCO)
+{
+	Name (_HID, "GOOG000C")
+	Name (_UID, 1)
+	Name (_DDN, "Wilco EC Command Device")
+
+	Method (_STA)
+	{
+		Return (0xf)
+	}
+
+	Name (_CRS, ResourceTemplate ()
+	{
+		IO (Decode16,
+		    CONFIG_EC_BASE_HOST_DATA,
+		    CONFIG_EC_BASE_HOST_DATA,
+		    4, 4)
+		IO (Decode16,
+		    CONFIG_EC_BASE_HOST_COMMAND,
+		    CONFIG_EC_BASE_HOST_COMMAND,
+		    4, 4)
+		IO (Decode16,
+		    CONFIG_EC_BASE_PACKET,
+		    CONFIG_EC_BASE_PACKET,
+		    16, 16)
+	})
+
+	Name (_PRS, ResourceTemplate ()
+	{
+		StartDependentFn (0, 0) {
+			IO (Decode16,
+			    CONFIG_EC_BASE_HOST_DATA,
+			    CONFIG_EC_BASE_HOST_DATA,
+			    4, 4)
+			IO (Decode16,
+			    CONFIG_EC_BASE_HOST_COMMAND,
+			    CONFIG_EC_BASE_HOST_COMMAND,
+			    4, 4)
+			IO (Decode16,
+			    CONFIG_EC_BASE_PACKET,
+			    CONFIG_EC_BASE_PACKET,
+			    16, 16)
+		}
+		EndDependentFn ()
+	})
+}
diff --git a/src/ec/google/wilco/acpi/ec_ram.asl b/src/ec/google/wilco/acpi/ec_ram.asl
new file mode 100644
index 0000000000..ffa0c9fa28
--- /dev/null
+++ b/src/ec/google/wilco/acpi/ec_ram.asl
@@ -0,0 +1,127 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Name (RD, 0)
+Name (WR, 1)
+
+/*
+ * EC RAM READ
+ */
+
+Name (P1ST, Package () { 0x00, 0xff, RD })	/* PmSt1 */
+Name (P1AC, Package () { 0x00, 0x01, RD })	/* PmSt1_AC_AVAIL */
+Name (P1BA, Package () { 0x00, 0x02, RD })	/* PmSt1_BAT_AVAIL */
+Name (P1L1, Package () { 0x00, 0x04, RD })	/* PmSt1_LOBAT1 */
+Name (P1L2, Package () { 0x00, 0x08, RD })	/* PmSt1_LOBAT2 */
+Name (P1LC, Package () { 0x00, 0x10, RD })	/* PmSt1_LID_CL */
+Name (P1OT, Package () { 0x00, 0x40, RD })	/* PmSt1_OVERTEMP */
+
+Name (P2ST, Package () { 0x01, 0xff, RD })	/* PmSt2 */
+name (P2PB, Package () { 0x01, 0x04, RD })	/* PmSt2_PWRB_PRESSED */
+
+Name (P3ST, Package () { 0x02, 0xff, RD })	/* PmSt3 */
+Name (P3B1, Package () { 0x02, 0x04, RD })	/* PmSt3_BAT1_PRES */
+Name (P3B2, Package () { 0x02, 0x08, RD })	/* PmSt3_BAT2_PRES */
+Name (P3FB, Package () { 0x02, 0x40, RD })	/* PmSt3_FORCE_BOM */
+Name (P3FT, Package () { 0x02, 0x80, RD })	/* PmSt3_FORCE_THROTTLE */
+
+Name (P4ST, Package () { 0x03, 0xff, RD })	/* PmSt4 */
+Name (P4C1, Package () { 0x03, 0x01, RD })	/* PmSt4_BAT1_CHG */
+Name (P4C2, Package () { 0x03, 0x02, RD })	/* PmSt4_BAT2_CHG */
+Name (P4P1, Package () { 0x03, 0x04, RD })	/* PmSt4_BAT1_PWR */
+Name (P4P2, Package () { 0x03, 0x08, RD })	/* PmSt4_BAT2_PWR */
+Name (P4BI, Package () { 0x03, 0x10, RD })	/* PmSt4_BAT_IDLE */
+Name (P4PS, Package () { 0x03, 0x20, RD })	/* PmSt4_PANEL_STATE */
+Name (P4CD, Package () { 0x03, 0x40, RD })	/* PmSt4_BATD_CHG */
+
+Name (P5ST, Package () { 0x04, 0xff, RD })	/* PmSt5 */
+Name (P5U1, Package () { 0x04, 0x01, RD })	/* PmSt5_BAT1_UPDATE */
+
+Name (P6ST, Package () { 0x05, 0xff, RD })	/* PmSt6 */
+Name (P6AC, Package () { 0x05, 0x08, RD })	/* PmSt6_AC_UPDATE */
+
+Name (ACEX, Package () { 0x06, 0x01, RD })	/* AC Present */
+Name (BTEX, Package () { 0x06, 0x02, RD })	/* Battery Present */
+Name (BTSC, Package () { 0x06, 0x04, RD })	/* Battery Status Changed */
+
+Name (EVT1, Package () { 0x07, 0xff, RD })	/* Event 1 */
+Name (E1PB, Package () { 0x07, 0x01, RD })	/* Power Button */
+Name (E1LD, Package () { 0x07, 0x04, RD })	/* Lid */
+Name (E1PW, Package () { 0x07, 0x08, RD })	/* Power */
+Name (E1SB, Package () { 0x07, 0x40, RD })	/* Sleep Button */
+Name (E1SS, Package () { 0x07, 0x80, RD })	/* SMI-SCI */
+
+Name (EVT2, Package () { 0x08, 0xff, RD })	/* Event 2 */
+Name (E2BS, Package () { 0x08, 0x02, RD })	/* BSS */
+Name (E2OR, Package () { 0x08, 0x04, RD })	/* Orientation */
+Name (E2QS, Package () { 0x08, 0x08, RD })	/* Quickset */
+Name (E2PN, Package () { 0x08, 0x20, RD })	/* Panel */
+Name (E2DP, Package () { 0x08, 0x40, RD })	/* Display Port */
+Name (E2VT, Package () { 0x08, 0x80, RD })	/* Video Throttle */
+
+Name (WAKE, Package () { 0x09, 0xff, RD })	/* Wake Events */
+Name (WPWB, Package () { 0x09, 0x01, RD })	/* Wake: Power Button */
+Name (WLID, Package () { 0x09, 0x02, RD })	/* Wake: Lid */
+Name (WUSB, Package () { 0x09, 0x04, RD })	/* Wake: USB */
+Name (WPME, Package () { 0x09, 0x10, RD })	/* Wake: PME */
+Name (WRTC, Package () { 0x09, 0x20, RD })	/* Wake: RTC */
+Name (WBAT, Package () { 0x09, 0x80, RD })	/* Wake: Low Battery */
+
+Name (EVT3, Package () { 0x0b, 0xff, RD })	/* Event 3 */
+Name (EVT4, Package () { 0x0c, 0xff, RD })	/* Event 4 */
+
+Name (BCST, Package () { 0x10, 0xff, RD })	/* BCACHE: BST */
+Name (BCRS, Package () { 0x11, 0xff, RD })	/* BCACHE: RSOC */
+Name (BCCL, Package () { 0x12, 0xffff, RD })	/* BCACHE: Current */
+Name (BCVL, Package () { 0x14, 0xffff, RD })	/* BCACHE: Voltage */
+Name (BCYL, Package () { 0x16, 0xffff, RD })	/* BCACHE: Capacity */
+Name (BCTL, Package () { 0x18, 0xffff, RD })	/* BCACHE: Temp */
+Name (BCML, Package () { 0x1a, 0xffff, RD })	/* BCACHE: Ma */
+Name (BSRL, Package () { 0x1c, 0xffff, RD })	/* BSTATIC: Max Error Low */
+Name (BSFL, Package () { 0x1e, 0xffff, RD })	/* BSTATIC: Full Cap Low */
+Name (BSCL, Package () { 0x20, 0xffff, RD })	/* BSTATIC: Design Cap Low */
+Name (BSVL, Package () { 0x22, 0xffff, RD })	/* BSTATIC: Design Volt Low */
+Name (BSDL, Package () { 0x24, 0xffff, RD })	/* BSTATIC: Mfg Date Low */
+Name (BSSL, Package () { 0x26, 0xffff, RD })	/* BSTATIC: Serial Number Low */
+Name (BSMN, Package () { 0x28, 0xff, RD })	/* BSTATIC: Manufacturer Name */
+Name (BSDC, Package () { 0x29, 0xff, RD })	/* BSTATIC: Device Chemistry */
+Name (BSBS, Package () { 0x2a, 0xff, RD })	/* BSTATIC: Battery String */
+
+Name (QSEC, Package () { 0x2b, 0xff, RD })	/* QuickSet Event Count */
+Name (QSEB, Package () { 0x2c, 0xff, RD })	/* QuickSet Event Byte */
+
+Name (ORST, Package () { 0x39, 0xff, RD })	/* Orientation State */
+Name (OREV, Package () { 0x3a, 0xff, RD })	/* Orientation Events */
+Name (OECH, Package () { 0x3a, 0x01, RD })	/* Event: Orientation */
+Name (OERL, Package () { 0x3a, 0x02, RD })	/* Event: Rotation Lock */
+
+Name (BCCY, Package () { 0x3e, 0xffff, RD })	/* BCACHE: Cycle Count */
+
+Name (APWR, Package () { 0x47, 0xff, RD })	/* POWER: Full Status */
+Name (APAC, Package () { 0x47, 0x01, RD })	/* POWER: AC */
+Name (APB1, Package () { 0x47, 0x02, RD })	/* POWER: Main Battery */
+Name (APC1, Package () { 0x47, 0x04, RD })	/* POWER: Main Batt Status */
+
+/*
+ * EC RAM WRITE
+ */
+
+Name (FPTS, Package () { 0x02, 0xff, WR })	/* EC _PTS */
+Name (BSEL, Package () { 0x03, 0xff, WR })	/* Battery Select */
+Name (SSEL, Package () { 0x04, 0xff, WR })	/* Battery String Select */
+Name (ERDY, Package () { 0x05, 0xff, WR })	/* EC Ready */
+Name (FWAK, Package () { 0x06, 0xff, WR })	/* EC _WAK */
+Name (PS2M, Package () { 0x20, 0xff, WR })	/* EC PS/2 Mouse Emulation */
diff --git a/src/ec/google/wilco/acpi/lid.asl b/src/ec/google/wilco/acpi/lid.asl
new file mode 100644
index 0000000000..818e1355c0
--- /dev/null
+++ b/src/ec/google/wilco/acpi/lid.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Device (LID)
+{
+	Name (_HID, EisaId ("PNP0C0D"))
+	Name (_UID, 1)
+	Name (_STA, 0xf)
+
+	Method (_LID, 0, NotSerialized)
+	{
+		Return (R (P1LC))
+	}
+}
diff --git a/src/ec/google/wilco/acpi/platform.asl b/src/ec/google/wilco/acpi/platform.asl
new file mode 100644
index 0000000000..802c8f780f
--- /dev/null
+++ b/src/ec/google/wilco/acpi/platform.asl
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Call from \_SB._PTS() */
+Method (PTS, 1, Serialized)
+{
+	Printf ("EC _PTS")
+	W (FPTS, Arg0)
+}
+
+/* Call from \_SB._WAK() */
+Method (WAK, 1, Serialized)
+{
+	Printf ("EC _WAK")
+	W (FWAK, Arg0)
+}