diff options
author | Aaron Durbin <adurbin@chromium.org> | 2016-04-21 14:06:17 -0500 |
---|---|---|
committer | Aaron Durbin <adurbin@chromium.org> | 2016-05-02 20:03:34 +0200 |
commit | a6e9051bc6843bb8f42df9c29cd254914ece93b4 (patch) | |
tree | a7ad973819f8c0388977b20034c94bc68eb95598 | |
parent | a2118a21c9e6a65bd90481f222cb436509b3e0bb (diff) |
lib/coreboot_table: use the architecture dependent table size
Utilize the architecture dependent coreboot table size value
from <arch/cbconfig.h>
Change-Id: I80d51a5caf7c455b0b47c380e1d79cf522502a4c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14455
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
-rw-r--r-- | src/Kconfig | 9 | ||||
-rw-r--r-- | src/arch/arm/include/arch/cbconfig.h | 2 | ||||
-rw-r--r-- | src/arch/arm64/include/arch/cbconfig.h | 2 | ||||
-rw-r--r-- | src/arch/mips/include/arch/cbconfig.h | 2 | ||||
-rw-r--r-- | src/arch/power8/include/arch/cbconfig.h | 2 | ||||
-rw-r--r-- | src/arch/riscv/include/arch/cbconfig.h | 2 | ||||
-rw-r--r-- | src/arch/x86/include/arch/cbconfig.h | 2 | ||||
-rw-r--r-- | src/lib/coreboot_table.c | 3 |
8 files changed, 14 insertions, 10 deletions
diff --git a/src/Kconfig b/src/Kconfig index b656bbfa22..f9bd661e05 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -658,15 +658,6 @@ config ACPI_NHLT help Build support for NHLT (non HD Audio) ACPI table generation. - -config COREBOOT_TABLE_SIZE - hex - default 0x8000 if ARCH_X86 - default 0x2000 if !ARCH_X86 - help - The amount of memory to reserve for the coreboot tables in - cbmem. - #These Options are here to avoid "undefined" warnings. #The actual selection and help texts are in the following menu. diff --git a/src/arch/arm/include/arch/cbconfig.h b/src/arch/arm/include/arch/cbconfig.h index 7bf9452562..9467f52646 100644 --- a/src/arch/arm/include/arch/cbconfig.h +++ b/src/arch/arm/include/arch/cbconfig.h @@ -23,4 +23,6 @@ * to have the same name across all architectures. */ +#define COREBOOT_TABLE_SIZE 0x2000 + #endif diff --git a/src/arch/arm64/include/arch/cbconfig.h b/src/arch/arm64/include/arch/cbconfig.h index 7bf9452562..9467f52646 100644 --- a/src/arch/arm64/include/arch/cbconfig.h +++ b/src/arch/arm64/include/arch/cbconfig.h @@ -23,4 +23,6 @@ * to have the same name across all architectures. */ +#define COREBOOT_TABLE_SIZE 0x2000 + #endif diff --git a/src/arch/mips/include/arch/cbconfig.h b/src/arch/mips/include/arch/cbconfig.h index 7bf9452562..9467f52646 100644 --- a/src/arch/mips/include/arch/cbconfig.h +++ b/src/arch/mips/include/arch/cbconfig.h @@ -23,4 +23,6 @@ * to have the same name across all architectures. */ +#define COREBOOT_TABLE_SIZE 0x2000 + #endif diff --git a/src/arch/power8/include/arch/cbconfig.h b/src/arch/power8/include/arch/cbconfig.h index 7bf9452562..9467f52646 100644 --- a/src/arch/power8/include/arch/cbconfig.h +++ b/src/arch/power8/include/arch/cbconfig.h @@ -23,4 +23,6 @@ * to have the same name across all architectures. */ +#define COREBOOT_TABLE_SIZE 0x2000 + #endif diff --git a/src/arch/riscv/include/arch/cbconfig.h b/src/arch/riscv/include/arch/cbconfig.h index 7bf9452562..9467f52646 100644 --- a/src/arch/riscv/include/arch/cbconfig.h +++ b/src/arch/riscv/include/arch/cbconfig.h @@ -23,4 +23,6 @@ * to have the same name across all architectures. */ +#define COREBOOT_TABLE_SIZE 0x2000 + #endif diff --git a/src/arch/x86/include/arch/cbconfig.h b/src/arch/x86/include/arch/cbconfig.h index 7bf9452562..78a5940c6a 100644 --- a/src/arch/x86/include/arch/cbconfig.h +++ b/src/arch/x86/include/arch/cbconfig.h @@ -23,4 +23,6 @@ * to have the same name across all architectures. */ +#define COREBOOT_TABLE_SIZE 0x8000 + #endif diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 58c6f48cbf..4dbac1930d 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <arch/cbconfig.h> #include <console/console.h> #include <console/uart.h> #include <ip_checksum.h> @@ -560,7 +561,7 @@ void write_tables(void) uintptr_t cbtable_start; uintptr_t cbtable_end; size_t cbtable_size; - const size_t max_table_size = CONFIG_COREBOOT_TABLE_SIZE; + const size_t max_table_size = COREBOOT_TABLE_SIZE; cbtable_start = (uintptr_t)cbmem_add(CBMEM_ID_CBTABLE, max_table_size); |