src/mainboard/lenovo-winent: Add space around operators

Change-Id: Iab2a879ebdea9d93ef5eb7e3abf875036c1e1cb4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16641 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
author: Elyes HAOUAS <ehaouas@noos.fr> 2016-09-19 09:47:16 -0600
committer: Patrick Georgi <pgeorgi@google.com> 2016-09-20 21:55:12 +0200
commit: a5aad2ed68690d748c650f69a2e39f91a7b02608 (patch)
tree: 7ad419bc13bcf13e546481558aa1a4c923821c07
parent: 531b87ac4e8038aedf9c44c29fe2c1fc31adb346 (diff)
81 files changed, 392 insertions, 392 deletions
diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c
index 79c093fb81..a8cf5c5dea 100644
--- a/src/mainboard/lippert/frontrunner-af/mainboard.c
+++ b/src/mainboard/lippert/frontrunner-af/mainboard.c
@@ -31,7 +31,7 @@
 
 /* Init SIO GPIOs. */
 #define SIO_RUNTIME_BASE 0x0E00
-static const u16 sio_init_table[] = { // hi=offset, lo=value
+static const u16 sio_init_table[] = { // hi = offset, lo = value
 	0x4BA0, // GP1x: COM1/2 control   = RS232, no term, max 115200
 	0x2300, // GP10: COM1 termination = push/pull output
 	0x2400, // GP11: COM2 termination = push/pull output
@@ -70,7 +70,7 @@ static const u16 sio_init_table[] = { // hi=offset, lo=value
 static int smb_write_blk(u8 slave, u8 command, u8 length, const u8 *data)
 {
 	__outbyte(SMB0_STATUS, 0x1E);		// clear error status
-	__outbyte(SMB0_ADDRESS, slave & ~1);	// slave addr + direction=out
+	__outbyte(SMB0_ADDRESS, slave & ~1);	// slave addr + direction = out
 	__outbyte(SMB0_HOSTCMD, command);	// or destination offset
 	__outbyte(SMB0_DATA0, length);		// sent before data
 	__inbyte(SMB0_CONTROL);			// reset block data array
diff --git a/src/mainboard/lippert/frontrunner/irq_tables.c b/src/mainboard/lippert/frontrunner/irq_tables.c
index 2e0d9d624a..a8f7e364f7 100644
--- a/src/mainboard/lippert/frontrunner/irq_tables.c
+++ b/src/mainboard/lippert/frontrunner/irq_tables.c
@@ -23,7 +23,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_VERSION,    /* u16 version   */
 	32+16*CONFIG_IRQ_SLOT_COUNT,	 /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
 	0x00,		 /* Where the interrupt router lies (bus) */
-	(0x12<<3)|0x0,   /* Where the interrupt router lies (dev) */
+	(0x12 << 3)|0x0,   /* Where the interrupt router lies (dev) */
 	0x800,		 /* IRQs devoted exclusively to PCI usage */
 	0x1078,		 /* Vendor */
 	0x2,		 /* Device */
@@ -31,9 +31,9 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
 	0xdf,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
 	{
-		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x0e<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
-		{0x00,(0x0f<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0},
+		/* bus,       dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,(0x0e << 3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
+		{0x00,(0x0f << 3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0},
 	}
 };
 unsigned long write_pirq_routing_table(unsigned long addr)
diff --git a/src/mainboard/lippert/hurricane-lx/mainboard.c b/src/mainboard/lippert/hurricane-lx/mainboard.c
index ffd20d00cf..3d32113858 100644
--- a/src/mainboard/lippert/hurricane-lx/mainboard.c
+++ b/src/mainboard/lippert/hurricane-lx/mainboard.c
@@ -31,7 +31,7 @@
 	#define SIO_GP1X_CONFIG 0x00
 #endif
 
-static const u16 ec_init_table[] = { /* hi=data, lo=index */
+static const u16 ec_init_table[] = { /* hi = data, lo = index */
 	0x1900,		/* Enable monitoring */
 	0x0351,		/* TMPIN1,2 diode mode, TMPIN3 off */
 	0x805C,		/* Unlock zero adjust */
diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c
index 0c9e03a4cd..7e3288f81e 100644
--- a/src/mainboard/lippert/hurricane-lx/romstage.c
+++ b/src/mainboard/lippert/hurricane-lx/romstage.c
@@ -76,7 +76,7 @@ static int smc_send_config(unsigned char config_data)
 #include "cpu/amd/geode_lx/syspreinit.c"
 #include "cpu/amd/geode_lx/msrinit.c"
 
-static const u16 sio_init_table[] = { // hi=data, lo=index
+static const u16 sio_init_table[] = { // hi = data, lo = index
 	0x042C,		// disable ATXPG; VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 enabled
 	0x1423,		// don't delay PoWeROK1/2
 	0x9072,		// watchdog triggers PWROK, counts seconds
@@ -84,7 +84,7 @@ static const u16 sio_init_table[] = { // hi=data, lo=index
 	0x0073, 0x0074,	// disarm watchdog by changing 56 s timeout to 0
 #endif
 	0xBF25, 0x172A, 0xF326,	// select GPIO function for most pins
-	0xBF27, 0xFF28, 0x2D29,	// (GP36=FAN_CTL3 (PWM), GP23,22,16,15=SPI, GP13=PWROK1)
+	0xBF27, 0xFF28, 0x2D29,	// (GP36 = FAN_CTL3 (PWM), GP23,22,16,15 = SPI, GP13 = PWROK1)
 	0x66B8, 0x0CB9,	// enable pullups on SPI, RS485_EN
 	0x07C0,		// enable Simple-I/O for GP12-10= RS485_EN2,1, WD_ACTIVE
 	0x06C8,		// config GP12,11 as output, GP10 as input
diff --git a/src/mainboard/lippert/literunner-lx/mainboard.c b/src/mainboard/lippert/literunner-lx/mainboard.c
index 1a569e2b58..e4084b5cbc 100644
--- a/src/mainboard/lippert/literunner-lx/mainboard.c
+++ b/src/mainboard/lippert/literunner-lx/mainboard.c
@@ -34,7 +34,7 @@
 /* Bit0 enables COM3's transceiver, bit1 disables the RS485 receiver (e.g. for IR). */
 #define SIO_GP2X_CONFIG 0x00
 
-static const u16 ec_init_table[] = { /* hi=data, lo=index */
+static const u16 ec_init_table[] = { /* hi = data, lo = index */
 	0x1900,		/* Enable monitoring */
 	0x3050,		/* VIN4,5 enabled */
 	0x0351,		/* TMPIN1,2 diode mode, TMPIN3 off */
diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c
index efe322c019..2f6aa469a0 100644
--- a/src/mainboard/lippert/literunner-lx/romstage.c
+++ b/src/mainboard/lippert/literunner-lx/romstage.c
@@ -115,7 +115,7 @@ static int smc_send_config(unsigned char config_data)
 #include "cpu/amd/geode_lx/syspreinit.c"
 #include "cpu/amd/geode_lx/msrinit.c"
 
-static const u16 sio_init_table[] = { // hi=data, lo=index
+static const u16 sio_init_table[] = { // hi = data, lo = index
 	0x072C,		// VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 internal
 	0x1423,		// don't delay PoWeROK1/2
 	0x9072,		// watchdog triggers PWROK, counts seconds
@@ -123,7 +123,7 @@ static const u16 sio_init_table[] = { // hi=data, lo=index
 	0x0073, 0x0074,	// disarm watchdog by changing 56 s timeout to 0
 #endif
 	0xBF25, 0x172A, 0xF326,	// select GPIO function for most pins
-	0xFF27, 0xDF28, 0x2729,	// (GP45=SUSB, GP23,22,16,15=SPI, GP13=PWROK1)
+	0xFF27, 0xDF28, 0x2729,	// (GP45 = SUSB, GP23,22,16,15 = SPI, GP13 = PWROK1)
 	0x66B8, 0x0FB9,	// enable pullups on SPI, RS485_EN, COM3_R/TX_EN
 	0x07C0,		// enable Simple-I/O for GP12-10= RS485_EN2,1, LIVE_LED
 	0x03C1,		// enable Simple-I/O for GP21-20= COM3_RX_EN,TX_EN
@@ -131,7 +131,7 @@ static const u16 sio_init_table[] = { // hi=data, lo=index
 	0x07C8,		// config GP12-10 as output
 	0x03C9,		// config GP21-20 as output
 	0x2DF5,		// map Hw Monitor Thermal Output to GP55
-	0x08F8,		// map GP LED Blinking 1 to GP10=LIVE_LED (deactivate Simple I/O to use)
+	0x08F8,		// map GP LED Blinking 1 to GP10 = LIVE_LED (deactivate Simple I/O to use)
 };
 
 /* Early mainboard specific GPIO setup. */
diff --git a/src/mainboard/lippert/roadrunner-lx/mainboard.c b/src/mainboard/lippert/roadrunner-lx/mainboard.c
index cd83768598..1d35ebe464 100644
--- a/src/mainboard/lippert/roadrunner-lx/mainboard.c
+++ b/src/mainboard/lippert/roadrunner-lx/mainboard.c
@@ -31,7 +31,7 @@
 	#define SIO_GP1X_CONFIG 0x20
 #endif
 
-static const u16 ec_init_table[] = {	/* hi=data, lo=index */
+static const u16 ec_init_table[] = {	/* hi = data, lo = index */
 	0x1900,		/* Enable monitoring */
 	0x0351,		/* TMPIN1,2 diode mode, TMPIN3 off */
 	0x805C,		/* Unlock zero adjust */
diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c
index d70e2c1835..7e0e2a5e01 100644
--- a/src/mainboard/lippert/roadrunner-lx/romstage.c
+++ b/src/mainboard/lippert/roadrunner-lx/romstage.c
@@ -52,7 +52,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 #include "cpu/amd/geode_lx/syspreinit.c"
 #include "cpu/amd/geode_lx/msrinit.c"
 
-static const u16 sio_init_table[] = {	// hi=data, lo=index
+static const u16 sio_init_table[] = {	// hi = data, lo = index
 	0x1E2C,		// disable ATXPG; VIN6,FAN4/5,VIN3 enabled, VIN7 internal
 	0x1423,		// don't delay PoWeROK1/2 - triggers 2nd reset
 	0x9072,		// watchdog triggers PWROK, counts seconds
@@ -60,13 +60,13 @@ static const u16 sio_init_table[] = {	// hi=data, lo=index
 	0x0073, 0x0074,	// disarm watchdog by changing 56 s timeout to 0
 #endif
 	0xBF25, 0x372A, 0xF326, // select GPIO function for most pins
-	0xBF27, 0xFF28, 0x2529, // (GP36=FAN_CTL3, GP13=PWROK1)
+	0xBF27, 0xFF28, 0x2529, // (GP36 = FAN_CTL3, GP13 = PWROK1)
 	0x46B8, 0x0CB9,	// enable pullups on RS485_EN
 	0x36C0,		// enable Simple-I/O for GP15,14,12,11= LIVE_LED, WD_ACTIVE, RS485_EN2,1
 	0xFFC3,		// enable Simple-I/O for GP47-40 (GPIOs on Supervisory Connector)
 	0x26C8,		// config GP15,12,11 as output; GP14 as input
 	0x2DF5,		// map Hw Monitor Thermal Output to GP55
-	0x0DF8,		// map GP LED Blinking 1 to GP15=LIVE_LED (deactivate Simple-I/O to use)
+	0x0DF8,		// map GP LED Blinking 1 to GP15 = LIVE_LED (deactivate Simple-I/O to use)
 };
 
 /* Early mainboard specific GPIO setup. */
diff --git a/src/mainboard/lippert/spacerunner-lx/devicetree.cb b/src/mainboard/lippert/spacerunner-lx/devicetree.cb
index 8619e84b6a..5f5b15bbb6 100644
--- a/src/mainboard/lippert/spacerunner-lx/devicetree.cb
+++ b/src/mainboard/lippert/spacerunner-lx/devicetree.cb
@@ -21,7 +21,7 @@ chip northbridge/amd/lx
 			register "com2_enable"				= "0"
 			register "com2_address"				= "0x2E8"
 			register "com2_irq"				= "6"
-			register "unwanted_vpci[0]"			= "0x80007B00" # Audio: 1<<31 + Device 0x0F<<11 + Function 3<<8
+			register "unwanted_vpci[0]"			= "0x80007B00" # Audio: 1 << 31 + Device 0x0F << 11 + Function 3 << 8
 			register "unwanted_vpci[1]"			= "0" # End of list has a zero
 			device pci 8.0 on end		# Slot4
 			device pci 9.0 on end		# Slot3
diff --git a/src/mainboard/lippert/spacerunner-lx/mainboard.c b/src/mainboard/lippert/spacerunner-lx/mainboard.c
index 4decd0e95e..b0bc74e9f6 100644
--- a/src/mainboard/lippert/spacerunner-lx/mainboard.c
+++ b/src/mainboard/lippert/spacerunner-lx/mainboard.c
@@ -31,7 +31,7 @@
 	#define SIO_GP1X_CONFIG 0x01
 #endif
 
-static const u16 ec_init_table[] = { /* hi=data, lo=index */
+static const u16 ec_init_table[] = { /* hi = data, lo = index */
 	0x1900,		/* Enable monitoring */
 	0x3050,		/* VIN4,5 enabled */
 	0x0351,		/* TMPIN1,2 diode mode, TMPIN3 off */
diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c
index b3a13ad4b2..85503c547d 100644
--- a/src/mainboard/lippert/spacerunner-lx/romstage.c
+++ b/src/mainboard/lippert/spacerunner-lx/romstage.c
@@ -116,7 +116,7 @@ static int smc_send_config(unsigned char config_data)
 #include "cpu/amd/geode_lx/syspreinit.c"
 #include "cpu/amd/geode_lx/msrinit.c"
 
-static const u16 sio_init_table[] = { // hi=data, lo=index
+static const u16 sio_init_table[] = { // hi = data, lo = index
 	0x072C,		// VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 internal
 	0x1423,		// don't delay PoWeROK1/2
 	0x9072,		// watchdog triggers PWROK, counts seconds
@@ -124,12 +124,12 @@ static const u16 sio_init_table[] = { // hi=data, lo=index
 	0x0073, 0x0074,	// disarm watchdog by changing 56 s timeout to 0
 #endif
 	0xBF25, 0x172A, 0xF326,	// select GPIO function for most pins
-	0xFF27, 0xDF28, 0x2729,	// (GP45=SUSB, GP23,22,16,15=SPI, GP13=PWROK1)
+	0xFF27, 0xDF28, 0x2729,	// (GP45 = SUSB, GP23,22,16,15 = SPI, GP13 = PWROK1)
 	0x66B8, 0x0CB9,	// enable pullups on SPI, RS485_EN
 	0x07C0,		// enable Simple-I/O for GP12-10= RS485_EN2,1, LIVE_LED
 	0x07C8,		// config GP12-10 as output
 	0x2DF5,		// map Hw Monitor Thermal Output to GP55
-	0x08F8,		// map GP LED Blinking 1 to GP10=LIVE_LED (deactivate Simple I/O to use)
+	0x08F8,		// map GP LED Blinking 1 to GP10 = LIVE_LED (deactivate Simple I/O to use)
 };
 
 /* Early mainboard specific GPIO setup. */
diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c
index b9c532f4d8..6b51fd2e97 100644
--- a/src/mainboard/lippert/toucan-af/mainboard.c
+++ b/src/mainboard/lippert/toucan-af/mainboard.c
@@ -39,7 +39,7 @@
 static int smb_write_blk(u8 slave, u8 command, u8 length, const u8 *data)
 {
 	__outbyte(SMB0_STATUS, 0x1E);		// clear error status
-	__outbyte(SMB0_ADDRESS, slave & ~1);	// slave addr + direction=out
+	__outbyte(SMB0_ADDRESS, slave & ~1);	// slave addr + direction = out
 	__outbyte(SMB0_HOSTCMD, command);	// or destination offset
 	__outbyte(SMB0_DATA0, length);		// sent before data
 	__inbyte(SMB0_CONTROL);			// reset block data array
@@ -96,7 +96,7 @@ static void init(struct device *dev)
 	 * effect a power cycle and switch to the alternate BIOS chip.
 	 * Should be done as late as possible. */
 	printk(BIOS_INFO, "Sending BIOS alive message\n");
-	const u8 i_am_alive[] = { 0x03 }; //bit2=SEL_DP0: 0=DDI2, 1=LVDS
+	const u8 i_am_alive[] = { 0x03 }; //bit2 = SEL_DP0: 0 = DDI2, 1 = LVDS
 	if ((i = smb_write_blk(0x50, 0x25, sizeof(i_am_alive), i_am_alive)))
 		printk(BIOS_ERR, "smb_write_blk failed: %d\n", i);
 
diff --git a/src/mainboard/msi/ms6119/irq_tables.c b/src/mainboard/msi/ms6119/irq_tables.c
index 496c01fdb2..2b9f7f49c9 100644
--- a/src/mainboard/msi/ms6119/irq_tables.c
+++ b/src/mainboard/msi/ms6119/irq_tables.c
@@ -29,14 +29,14 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
 	0x9c,			/* Checksum */
 	{
-		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x0e<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0},
-		{0x00,(0x10<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0},
-		{0x00,(0x12<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0},
-		{0x00,(0x14<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0},
-		{0x00,(0x07<<3)|0x1, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
-		{0x00,(0x07<<3)|0x2, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
-		{0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
+		/* bus,       dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,(0x0e << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0},
+		{0x00,(0x10 << 3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0},
+		{0x00,(0x12 << 3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0},
+		{0x00,(0x14 << 3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0},
+		{0x00,(0x07 << 3)|0x1, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
+		{0x00,(0x07 << 3)|0x2, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
+		{0x00,(0x01 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
 	}
 };
 
diff --git a/src/mainboard/msi/ms6147/irq_tables.c b/src/mainboard/msi/ms6147/irq_tables.c
index 2590bb9c31..46e32687e8 100644
--- a/src/mainboard/msi/ms6147/irq_tables.c
+++ b/src/mainboard/msi/ms6147/irq_tables.c
@@ -29,15 +29,15 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
 	0x20,			/* Checksum */
 	{
-		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x0e<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0},
-		{0x00,(0x10<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0},
-		{0x00,(0x12<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0},
-		{0x00,(0x14<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0},
-		{0x00,(0x00<<3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, /* North bridge */
-		{0x00,(0x07<<3)|0x1, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, /* IDE */
-		{0x00,(0x07<<3)|0x2, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, /* UHCI */
-		{0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, /* AGP bridge */
+		/* bus,       dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,(0x0e << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0},
+		{0x00,(0x10 << 3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0},
+		{0x00,(0x12 << 3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0},
+		{0x00,(0x14 << 3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0},
+		{0x00,(0x00 << 3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, /* North bridge */
+		{0x00,(0x07 << 3)|0x1, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, /* IDE */
+		{0x00,(0x07 << 3)|0x2, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, /* UHCI */
+		{0x00,(0x01 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, /* AGP bridge */
 	}
 };
 
diff --git a/src/mainboard/msi/ms6178/irq_tables.c b/src/mainboard/msi/ms6178/irq_tables.c
index 2daf2558f2..fae5bcf998 100644
--- a/src/mainboard/msi/ms6178/irq_tables.c
+++ b/src/mainboard/msi/ms6178/irq_tables.c
@@ -29,11 +29,11 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
 	0x1a,			/* Checksum */
 	{
-		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x1e<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0},
-		{0x00,(0x10<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0},
-		{0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
-		{0x00,(0x1f<<3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
+		/* bus,       dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,(0x1e << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0},
+		{0x00,(0x10 << 3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0},
+		{0x00,(0x01 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
+		{0x00,(0x1f << 3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
 	}
 };
 
diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c
index 775fdc6c2d..fccb200b7a 100644
--- a/src/mainboard/msi/ms9185/mptable.c
+++ b/src/mainboard/msi/ms9185/mptable.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2001 Eric W.Biederman<ebiderman@lnxi.com>
+ * Copyright (C) 2001 Eric W.Biederman <ebiderman@lnxi.com>
  *
  * Copyright (C) 2006 AMD
  * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
@@ -54,7 +54,7 @@ static void *smp_write_config_table(void *v)
         {
 		device_t dev = 0;
                struct resource *res;
-               for(i=0; i<3; i++) {
+               for(i = 0; i < 3; i++) {
                        dev = dev_find_device(0x1166, 0x0235, dev);
                        if (dev) {
                                res = find_resource(dev, PCI_BASE_ADDRESS_0);
@@ -76,11 +76,11 @@ static void *smp_write_config_table(void *v)
 
 //SATA
        outb(0x07, 0xc00); outb(0x0f, 0xc01);
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xf);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0xf);
 
 //USB
        outb(0x01, 0xc00); outb(0x0a, 0xc01);
-        for(i=0;i<3;i++) {
+        for(i = 0; i < 3; i++) {
                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, m->apicid_bcm5785[0], 0xa); //
         }
 
@@ -94,52 +94,52 @@ static void *smp_write_config_table(void *v)
                 if(dev) {
                         uint32_t dword;
                         dword = pci_read_config32(dev, 0x6c);
-                        dword |= (1<<4); // enable interrupts
+                        dword |= (1 << 4); // enable interrupts
                         pci_write_config32(dev, 0x6c, dword);
                 }
                 }
 
 //First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0
        // AIC 8130 Galileo Technology...
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (6<<2)|i, m->apicid_bcm5785[1], 2 + (1+i)%4); //
+        for(i = 0; i < 4; i++) {
+                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (6 << 2)|i, m->apicid_bcm5785[1], 2 + (1+i)%4); //
         }
 
 
 //pci slot (on bcm5785)
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (5<<2)|i, m->apicid_bcm5785[1], 8+i%4); //
+        for(i = 0; i < 4; i++) {
+                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (5 << 2)|i, m->apicid_bcm5785[1], 8+i%4); //
         }
 
 
 //onboard ati
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (4<<2)|0, m->apicid_bcm5785[1], 0x1);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (4 << 2)|0, m->apicid_bcm5785[1], 0x1);
 
 //PCI-X on bcm5780
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[1], (4<<2)|i, m->apicid_bcm5785[1], 2 + (0+i)%4); //
+        for(i = 0; i < 4; i++) {
+                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[1], (4 << 2)|i, m->apicid_bcm5785[1], 2 + (0+i)%4); //
         }
 
 //onboard Broadcom
-        for(i=0;i<2;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[2], (4<<2)|i, m->apicid_bcm5785[1], 0xa + (0+i)%4); //
+        for(i = 0; i < 2; i++) {
+                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[2], (4 << 2)|i, m->apicid_bcm5785[1], 0xa + (0+i)%4); //
         }
 
 
 // First PCI-E x8
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0<<2)|i, m->apicid_bcm5785[1], 0xe); //
+        for(i = 0; i < 4; i++) {
+                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0 << 2)|i, m->apicid_bcm5785[1], 0xe); //
         }
 
 
 // Second PCI-E x8
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[3], (0<<2)|i, m->apicid_bcm5785[1], 0xc); //
+        for(i = 0; i < 4; i++) {
+                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[3], (0 << 2)|i, m->apicid_bcm5785[1], 0xc); //
         }
 
 // Third PCI-E x1
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[4], (0<<2)|i, m->apicid_bcm5785[1], 0xd); //
+        for(i = 0; i < 4; i++) {
+                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[4], (0 << 2)|i, m->apicid_bcm5785[1], 0xd); //
         }
 
 /*Local Ints:  Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN#*/
diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c
index f6f6859ca7..16eb36f8ec 100644
--- a/src/mainboard/msi/ms9185/romstage.c
+++ b/src/mainboard/msi/ms9185/romstage.c
@@ -72,8 +72,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
-#define RC0 (0x10<<8)
-#define RC1 (0x01<<8)
+#define RC0 (0x10 << 8)
+#define RC1 (0x01 << 8)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
@@ -148,7 +148,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #if CONFIG_SET_FIDVID
         {
                 msr_t msr;
-                msr=rdmsr(0xc0010042);
+                msr = rdmsr(0xc0010042);
                 printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
         }
         enable_fid_change();
@@ -157,7 +157,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         // show final fid and vid
         {
                 msr_t msr;
-                msr=rdmsr(0xc0010042);
+                msr = rdmsr(0xc0010042);
                 printk(BIOS_DEBUG, "end   msr fid, vid %08x%08x\n", msr.hi, msr.lo);
         }
 #endif
@@ -181,7 +181,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 #if 0
        int i;
-       for(i=0;i<2;i++) {
+       for(i = 0; i < 2; i++) {
                activate_spd_rom(sysinfo->ctrl+i);
                dump_smbus_registers();
        }
diff --git a/src/mainboard/msi/ms9282/mptable.c b/src/mainboard/msi/ms9282/mptable.c
index cbad73536c..4619737cf3 100644
--- a/src/mainboard/msi/ms9282/mptable.c
+++ b/src/mainboard/msi/ms9282/mptable.c
@@ -99,15 +99,15 @@ static void *smp_write_config_table(void *v)
 //NIC2
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
 
-	for(j=7; j>=2; j--) {
+	for(j = 7; j >= 2; j--) {
 		if(!m->bus_mcp55[j]) continue;
-		for(i=0;i<4;i++) {
-			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
+		for(i = 0; i < 4; i++) {
+			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00 << 2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
 		}
 	}
 
-	for(j=0; j<1; j++)
-		for(i=0;i<4;i++) {
+	for(j = 0; j < 1; j++)
+		for(i = 0; i < 4; i++) {
 			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
 		}
 
diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c
index 04c5c3615b..7d360e3790 100644
--- a/src/mainboard/msi/ms9282/romstage.c
+++ b/src/mainboard/msi/ms9282/romstage.c
@@ -70,10 +70,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 //set GPIO to input mode
 #define MCP55_MB_SETUP \
-		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
-		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
-		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
-		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
+		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0 << 4)|(0 << 2)|(0 << 0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
+		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0 << 4)|(0 << 2)|(0 << 0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
+		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0 << 4)|(0 << 2)|(0 << 0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
+		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0 << 4)|(0 << 2)|(0 << 0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
 
 #include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
@@ -98,13 +98,13 @@ static void sio_setup(void)
 	pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
 
 	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
-	dword |= (1<<0);
+	dword |= (1 << 0);
 	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 }
 
 //CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1.
-#define RC0 (2<<8)
-#define RC1 (1<<8)
+#define RC0 (2 << 8)
+#define RC1 (1 << 8)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
diff --git a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c
index 39a24dd1f6..0614e1f126 100644
--- a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c
+++ b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c
@@ -70,7 +70,7 @@ void get_bus_conf(void)
 
 	printk(BIOS_SPEW, "get_bus_conf()\n");
 
-	if(get_bus_conf_done==1) return; //do it only once
+	if(get_bus_conf_done == 1) return; //do it only once
 
 	get_bus_conf_done = 1;
 
@@ -80,7 +80,7 @@ void get_bus_conf(void)
 	memset(m, 0, sizeof(struct mb_sysconf_t));
 
 	sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
-	for(i=0;i<sysconf.hc_possible_num; i++) {
+	for(i = 0; i < sysconf.hc_possible_num; i++) {
 		sysconf.pci1234[i] = pci1234x[i];
 		sysconf.hcdn[i] = hcdnx[i];
 	}
@@ -99,7 +99,7 @@ void get_bus_conf(void)
 			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
 		}
 
-		for(i=2; i<8;i++) {
+		for(i = 2; i < 8; i++) {
 			dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
 			if (dev) {
 				m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
@@ -112,10 +112,10 @@ void get_bus_conf(void)
 /*I/O APICs:	APIC ID	Version	State		Address*/
 	if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) {
 		apicid_base = get_apicid_base(1);
-		printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==1: apicid_base: %08x\n", apicid_base);
+		printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS == 1: apicid_base: %08x\n", apicid_base);
 	} else {
 		apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
-		printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==0: apicid_base: %08x\n", apicid_base);
+		printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS == 0: apicid_base: %08x\n", apicid_base);
 	}
 	m->apicid_mcp55 = apicid_base+0;
 }
diff --git a/src/mainboard/msi/ms9652_fam10/mptable.c b/src/mainboard/msi/ms9652_fam10/mptable.c
index eff19c7fc0..7d83c462d9 100644
--- a/src/mainboard/msi/ms9652_fam10/mptable.c
+++ b/src/mainboard/msi/ms9652_fam10/mptable.c
@@ -88,15 +88,15 @@ static void *smp_write_config_table(void *v)
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
 
-	for(j=7; j>=2; j--) {
+	for(j = 7; j >= 2; j--) {
 		if(!m->bus_mcp55[j]) continue;
-		for(i=0;i<4;i++) {
-			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
+		for(i = 0; i < 4; i++) {
+			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00 << 2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
 		}
 	}
 
-	for(j=0; j<1; j++)
-		for(i=0;i<4;i++) {
+	for(j = 0; j < 1; j++)
+		for(i = 0; i < 4; i++) {
 			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
 		}
 
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index 3af4785555..e22ec11b94 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -83,7 +83,7 @@ static void sio_setup(void)
 	pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
 
 	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
-	dword |= (1<<0);
+	dword |= (1 << 0);
 	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 }
 
@@ -200,7 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x3A);
 
 	/* show final fid and vid */
-	msr=rdmsr(0xc0010071);
+	msr = rdmsr(0xc0010071);
 	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 #endif
 	init_timer(); /* Need to use TMICT to synchronize FID/VID. */
diff --git a/src/mainboard/nvidia/l1_2pvv/mptable.c b/src/mainboard/nvidia/l1_2pvv/mptable.c
index d000b1a4e7..76bb73cafa 100644
--- a/src/mainboard/nvidia/l1_2pvv/mptable.c
+++ b/src/mainboard/nvidia/l1_2pvv/mptable.c
@@ -58,8 +58,8 @@ static void *smp_write_config_table(void *v)
 
 		/* Initialize interrupt mapping*/
 			dword = pci_read_config32(dev, 0x74);
-			dword &= ~(1<<15);
-			dword |= 1<<2;
+			dword &= ~(1 << 15);
+			dword |= 1 << 2;
 			pci_write_config32(dev, 0x74, dword);
 
 			dword = 0x43c6c643;
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index cfe5bebffa..d0966ee4fe 100644
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -81,11 +81,11 @@ static void sio_setup(void)
 	pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
 
 	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
-	dword |= (1<<0);
+	dword |= (1 << 0);
 	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 
 	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
-	dword |= (1<<16);
+	dword |= (1 << 16);
 	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
 }
 
@@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #if CONFIG_SET_FIDVID
 	{
 		msr_t msr;
-		msr=rdmsr(0xc0010042);
+		msr = rdmsr(0xc0010042);
 		printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
 	}
 	enable_fid_change();
@@ -158,7 +158,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	// show final fid and vid
 	{
 		msr_t msr;
-		msr=rdmsr(0xc0010042);
+		msr = rdmsr(0xc0010042);
 		printk(BIOS_DEBUG, "end   msr fid, vid %08x%08x\n", msr.hi, msr.lo);
 	}
 #endif
diff --git a/src/mainboard/rca/rm4100/irq_tables.c b/src/mainboard/rca/rm4100/irq_tables.c
index e8ef598ae3..e99adfcbc5 100644
--- a/src/mainboard/rca/rm4100/irq_tables.c
+++ b/src/mainboard/rca/rm4100/irq_tables.c
@@ -21,7 +21,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_VERSION,    /* u16 version   */
 	32+16*CONFIG_IRQ_SLOT_COUNT,	 /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
 	0x00,		 /* Where the interrupt router lies (bus) */
-	(0x1f<<3)|0x0,   /* Where the interrupt router lies (dev) */
+	(0x1f << 3)|0x0,   /* Where the interrupt router lies (dev) */
 	0,		 /* IRQs devoted exclusively to PCI usage */
 	0x8086,		 /* Vendor */
 	0x24c0,		 /* Device */
@@ -29,14 +29,14 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
 	0x07,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
 	{
-		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x02<<3)|0x0, {{0x60, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IGD VGA */
-		{0x00,(0x1d<<3)|0x0, {{0x60, 0x0ef8}, {0x63, 0x0ef8}, {0x62, 0x0ef8}, {0x6b, 0x00ef8}}, 0x0, 0x0}, /* [A] USB1, [B] USB2, [C] USB3, [D] EHCI */
-		{0x00,(0x1f<<3)|0x0, {{0x62, 0x0ef8}, {0x61, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IDE, [B] SMBUS, [B] AUDIO, [B] MODEM */
-		{0x01,(0x08<<3)|0x0, {{0x68, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] ETHERNET */
-		{0x01,(0x00<<3)|0x0, {{0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x0ef8}, {0x63, 0x00ef8}}, 0x1, 0x0}, /* PCI SLOT 1 */
-		{0x01,(0x01<<3)|0x0, {{0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x00ef8}}, 0x2, 0x0}, /* PCI SLOT 2 */
-		{0x01,(0x02<<3)|0x0, {{0x62, 0x0ef8}, {0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x00ef8}}, 0x3, 0x0}, /* PCI SLOT 3 */
+		/* bus,       dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,(0x02 << 3)|0x0, {{0x60, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IGD VGA */
+		{0x00,(0x1d << 3)|0x0, {{0x60, 0x0ef8}, {0x63, 0x0ef8}, {0x62, 0x0ef8}, {0x6b, 0x00ef8}}, 0x0, 0x0}, /* [A] USB1, [B] USB2, [C] USB3, [D] EHCI */
+		{0x00,(0x1f << 3)|0x0, {{0x62, 0x0ef8}, {0x61, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IDE, [B] SMBUS, [B] AUDIO, [B] MODEM */
+		{0x01,(0x08 << 3)|0x0, {{0x68, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] ETHERNET */
+		{0x01,(0x00 << 3)|0x0, {{0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x0ef8}, {0x63, 0x00ef8}}, 0x1, 0x0}, /* PCI SLOT 1 */
+		{0x01,(0x01 << 3)|0x0, {{0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x00ef8}}, 0x2, 0x0}, /* PCI SLOT 2 */
+		{0x01,(0x02 << 3)|0x0, {{0x62, 0x0ef8}, {0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x00ef8}}, 0x3, 0x0}, /* PCI SLOT 3 */
 	}
 };
 
diff --git a/src/mainboard/roda/rk886ex/irq_tables.c b/src/mainboard/roda/rk886ex/irq_tables.c
index 90ab6b0a3c..f6d02f8c45 100644
--- a/src/mainboard/roda/rk886ex/irq_tables.c
+++ b/src/mainboard/roda/rk886ex/irq_tables.c
@@ -21,7 +21,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_VERSION,    /* u16 version   */
 	32+16*18,	 /* There can be total 18 devices on the bus */
 	0x00,		 /* Where the interrupt router lies (bus) */
-	(0x1f<<3)|0x0,   /* Where the interrupt router lies (dev) */
+	(0x1f << 3)|0x0,   /* Where the interrupt router lies (dev) */
 	0,		 /* IRQs devoted exclusively to PCI usage */
 	0x8086,		 /* Vendor */
 	0x27b0,		 /* Device */
@@ -29,25 +29,25 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
 	0xf,		 /* u8 checksum. */
 	{
-		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
-		{0x00,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
-		{0x00,(0x1e<<3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
-		{0x00,(0x1f<<3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
-		{0x00,(0x1d<<3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
-		{0x00,(0x1b<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
-		{0x00,(0x1c<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
-		{0x04,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
-		{0x04,(0x01<<3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
-		{0x04,(0x02<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
-		{0x04,(0x03<<3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
-		{0x04,(0x04<<3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
-		{0x04,(0x05<<3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
-		{0x04,(0x06<<3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
-		{0x04,(0x09<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
-		{0x01,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168
-		{0x02,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
-		{0x03,(0x00<<3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
+		/* bus,       dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
+		{0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
+		{0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
+		{0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
+		{0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
+		{0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
+		{0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
+		{0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
+		{0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
+		{0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
+		{0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
+		{0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
+		{0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
+		{0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
+		{0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
+		{0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168
+		{0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
+		{0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
 	}
 };
 
diff --git a/src/mainboard/roda/rk886ex/m3885.c b/src/mainboard/roda/rk886ex/m3885.c
index 6a9b26c6fb..d5a2b70a6d 100644
--- a/src/mainboard/roda/rk886ex/m3885.c
+++ b/src/mainboard/roda/rk886ex/m3885.c
@@ -240,7 +240,7 @@ void m3885_configure_multikey(void)
 	m3885_set_variable(0x0c, kstate5_flags & ~(7 << 4));
 
 	/* Write Matrix to bank 0 */
-	for (i=0; i < ARRAY_SIZE(matrix); i++) {
+	for (i = 0; i < ARRAY_SIZE(matrix); i++) {
 		m3885_set_proc_ram(i + 0x80, matrix[i]);
 	}
 
@@ -257,7 +257,7 @@ void m3885_configure_multikey(void)
 			printk(BIOS_DEBUG, "M388x does not have a valid RAM offset (0x%x)\n", offs);
 		} else {
 			printk(BIOS_DEBUG, "Writing Fn-Table to M388x RAM offset 0x%x\n", offs);
-			for (i=0; i < ARRAY_SIZE(function_ram); i++) {
+			for (i = 0; i < ARRAY_SIZE(function_ram); i++) {
 				m3885_set_proc_ram(i + offs, function_ram[i]);
 			}
 		}
@@ -269,7 +269,7 @@ void m3885_configure_multikey(void)
 	m3885_set_variable(0x0c, kstate5_flags);
 	maxvars = m3885_get_variable(0x00);
 	printk(BIOS_DEBUG, "M388x has %d variables in original bank.\n", maxvars);
-	for (i=0; i<ARRAY_SIZE(variables); i+=3) {
+	for (i = 0; i < ARRAY_SIZE(variables); i+=3) {
 		if(variables[i + 0] > maxvars)
 			continue;
 		reg8 = m3885_get_variable(variables[i + 0]);
diff --git a/src/mainboard/roda/rk886ex/m3885.h b/src/mainboard/roda/rk886ex/m3885.h
index 0fb8294291..d2dcb146a7 100644
--- a/src/mainboard/roda/rk886ex/m3885.h
+++ b/src/mainboard/roda/rk886ex/m3885.h
@@ -21,50 +21,50 @@
 #define M3885_CMDAT2		0x06
 #define M3885_CMDAT3		0x07
 
-#define M3885_GPIO_LEVEL	(0<<7)
-#define M3885_GPIO_PULSE	(1<<7)
+#define M3885_GPIO_LEVEL	(0 << 7)
+#define M3885_GPIO_PULSE	(1 << 7)
 
-#define M3885_GPIO_READ		(0<<5)
-#define M3885_GPIO_SET		(1<<5)
-#define M3885_GPIO_CLEAR	(2<<5)
-#define M3885_GPIO_TOGGLE	(3<<5)
+#define M3885_GPIO_READ		(0 << 5)
+#define M3885_GPIO_SET		(1 << 5)
+#define M3885_GPIO_CLEAR	(2 << 5)
+#define M3885_GPIO_TOGGLE	(3 << 5)
 
-#define M3885_GPIO_P14		(0x00<<0)
-#define M3885_GPIO_P15		(0x01<<0)
-#define M3885_GPIO_P16		(0x02<<0)
-#define M3885_GPIO_P17		(0x03<<0)
+#define M3885_GPIO_P14		(0x00 << 0)
+#define M3885_GPIO_P15		(0x01 << 0)
+#define M3885_GPIO_P16		(0x02 << 0)
+#define M3885_GPIO_P17		(0x03 << 0)
 
-#define M3885_GPIO_P54		(0x04<<0)
-#define M3885_GPIO_P55		(0x05<<0)
-#define M3885_GPIO_P56		(0x06<<0)
-#define M3885_GPIO_P57		(0x07<<0)
+#define M3885_GPIO_P54		(0x04 << 0)
+#define M3885_GPIO_P55		(0x05 << 0)
+#define M3885_GPIO_P56		(0x06 << 0)
+#define M3885_GPIO_P57		(0x07 << 0)
 
-#define M3885_GPIO_P20		(0x08<<0)
-#define M3885_GPIO_P21		(0x09<<0)
-#define M3885_GPIO_P22		(0x0a<<0)
-#define M3885_GPIO_P23		(0x0b<<0)
-#define M3885_GPIO_P24		(0x0c<<0)
-#define M3885_GPIO_P25		(0x0d<<0)
-#define M3885_GPIO_P26		(0x0e<<0)
-#define M3885_GPIO_P27		(0x0f<<0)
+#define M3885_GPIO_P20		(0x08 << 0)
+#define M3885_GPIO_P21		(0x09 << 0)
+#define M3885_GPIO_P22		(0x0a << 0)
+#define M3885_GPIO_P23		(0x0b << 0)
+#define M3885_GPIO_P24		(0x0c << 0)
+#define M3885_GPIO_P25		(0x0d << 0)
+#define M3885_GPIO_P26		(0x0e << 0)
+#define M3885_GPIO_P27		(0x0f << 0)
 
-#define M3885_GPIO_P40		(0x10<<0)
-#define M3885_GPIO_P41		(0x11<<0)
-#define M3885_GPIO_P42		(0x12<<0)
-#define M3885_GPIO_P43		(0x13<<0)
-#define M3885_GPIO_P44		(0x14<<0)
-#define M3885_GPIO_P45		(0x15<<0)
-#define M3885_GPIO_P46		(0x16<<0)
-#define M3885_GPIO_P47		(0x17<<0)
+#define M3885_GPIO_P40		(0x10 << 0)
+#define M3885_GPIO_P41		(0x11 << 0)
+#define M3885_GPIO_P42		(0x12 << 0)
+#define M3885_GPIO_P43		(0x13 << 0)
+#define M3885_GPIO_P44		(0x14 << 0)
+#define M3885_GPIO_P45		(0x15 << 0)
+#define M3885_GPIO_P46		(0x16 << 0)
+#define M3885_GPIO_P47		(0x17 << 0)
 
-#define M3885_GPIO_P60		(0x18<<0)
-#define M3885_GPIO_P61		(0x19<<0)
-#define M3885_GPIO_P62		(0x1a<<0)
-#define M3885_GPIO_P63		(0x1b<<0)
-#define M3885_GPIO_P64		(0x1c<<0)
-#define M3885_GPIO_P65		(0x1d<<0)
-#define M3885_GPIO_P66		(0x1e<<0)
-#define M3885_GPIO_P67		(0x1f<<0)
+#define M3885_GPIO_P60		(0x18 << 0)
+#define M3885_GPIO_P61		(0x19 << 0)
+#define M3885_GPIO_P62		(0x1a << 0)
+#define M3885_GPIO_P63		(0x1b << 0)
+#define M3885_GPIO_P64		(0x1c << 0)
+#define M3885_GPIO_P65		(0x1d << 0)
+#define M3885_GPIO_P66		(0x1e << 0)
+#define M3885_GPIO_P67		(0x1f << 0)
 
 void m3885_configure_multikey(void);
 u8 m3885_gpio(u8 value);
diff --git a/src/mainboard/roda/rk886ex/mainboard.c b/src/mainboard/roda/rk886ex/mainboard.c
index 1ef24975fb..1959c3251c 100644
--- a/src/mainboard/roda/rk886ex/mainboard.c
+++ b/src/mainboard/roda/rk886ex/mainboard.c
@@ -35,7 +35,7 @@ static void backlight_enable(void)
 	/* P56 is Brightness Up, and it needs a Pulse instead of a
 	 * Level
 	 */
-	for (i=0; i < 28; i++) {
+	for (i = 0; i < 28; i++) {
 		//m3885_gpio(M3885_GPIO_PULSE|M3885_GPIO_SET|M3885_GPIO_P56);
 		m3885_gpio(M3885_GPIO_PULSE|M3885_GPIO_TOGGLE|M3885_GPIO_P56);
 	}
@@ -49,10 +49,10 @@ static void dump_runtime_registers(void)
 	int i;
 
 	printk(BIOS_DEBUG, "SuperIO runtime register block:\n");
-	for (i=0; i<0x10; i++)
+	for (i = 0; i < 0x10; i++)
 		printk(BIOS_DEBUG, "%02x ", i);
 	printk(BIOS_DEBUG, "\n");
-	for (i=0; i<0x10; i++)
+	for (i = 0; i < 0x10; i++)
 		printk(BIOS_DEBUG, "%02x ", inb(0x600 +i));
 	printk(BIOS_DEBUG, "\n");
 }
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index f3af5fa6a0..8de4665dd9 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -68,7 +68,7 @@ static void ich7_enable_lpc(void)
 {
 	int lpt_en = 0;
 	if (read_option(lpt, 0) != 0) {
-	       lpt_en = 1<<2; // enable LPT
+	       lpt_en = 1 << 2; // enable LPT
 	}
 	// Enable Serial IRQ
 	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
@@ -113,7 +113,7 @@ static void early_superio_config(void)
 {
 	device_t dev;
 
-	dev=PNP_DEV(0x2e, 0x00);
+	dev = PNP_DEV(0x2e, 0x00);
 
 	pnp_enter_ext_func_mode(dev);
 	pnp_write_register(dev, 0x01, 0x94); // Extended Parport modes
diff --git a/src/mainboard/samsung/lumpy/gpio.c b/src/mainboard/samsung/lumpy/gpio.c
index 8e8b936a4f..9d07e643cf 100644
--- a/src/mainboard/samsung/lumpy/gpio.c
+++ b/src/mainboard/samsung/lumpy/gpio.c
@@ -233,9 +233,9 @@ const struct pch_gpio_set2 pch_gpio_set2_level = {
 	.gpio41 = GPIO_LEVEL_LOW,
 	.gpio42 = GPIO_LEVEL_LOW,
 	.gpio43 = GPIO_LEVEL_LOW,
-	.gpio44 = GPIO_LEVEL_HIGH,	/* CTL2=1 for USB0 SDP */
-	.gpio45 = GPIO_LEVEL_LOW,	/* CTL3=0 for USB0 SDP */
-	.gpio46 = GPIO_LEVEL_HIGH,	/* CTL2=1 for USB1 SDP */
+	.gpio44 = GPIO_LEVEL_HIGH,	/* CTL2 = 1 for USB0 SDP */
+	.gpio45 = GPIO_LEVEL_LOW,	/* CTL3 = 0 for USB0 SDP */
+	.gpio46 = GPIO_LEVEL_HIGH,	/* CTL2 = 1 for USB1 SDP */
 	.gpio47 = GPIO_LEVEL_HIGH,	/* Enable USB0 */
 	.gpio48 = GPIO_LEVEL_LOW,	/* Disable Bluetooth */
 	.gpio49 = GPIO_LEVEL_LOW,
@@ -299,7 +299,7 @@ const struct pch_gpio_set3 pch_gpio_set3_level = {
 	.gpio70 = GPIO_LEVEL_HIGH,	/* WLAN out of reset */
 	.gpio71 = GPIO_LEVEL_HIGH,	/* WLAN power on */
 	.gpio72 = GPIO_LEVEL_LOW,
-	.gpio73 = GPIO_LEVEL_LOW,	/* USB1 CTL3=0 for SDP */
+	.gpio73 = GPIO_LEVEL_LOW,	/* USB1 CTL3 = 0 for SDP */
 	.gpio74 = GPIO_LEVEL_LOW,
 	.gpio75 = GPIO_LEVEL_LOW,
 };
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index 738f1ffe81..7f7999c786 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -144,9 +144,9 @@ static void setup_sio_gpios(void)
 	/*
 	 * GPIO45 as LED_POWER#
 	 */
-	it8772f_gpio_led(DUMMY_DEV, 4 /* set */, (0x1<<5) /* select */,
-		0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */,
-		(0x1<<5) /* output */, (0x1<<5) /* 1=Simple IO function */,
+	it8772f_gpio_led(DUMMY_DEV, 4 /* set */, (0x1 << 5) /* select */,
+		0x00 /* polarity: non-inverting */, 0x00 /* 0 = pulldown */,
+		(0x1 << 5) /* output */, (0x1 << 5) /* 1 = Simple IO function */,
 		SIO_GPIO_BLINK_GPIO45, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);
 
 	/*
diff --git a/src/mainboard/samsung/stumpy/smihandler.c b/src/mainboard/samsung/stumpy/smihandler.c
index 215af8fe7e..00148f2e22 100644
--- a/src/mainboard/samsung/stumpy/smihandler.c
+++ b/src/mainboard/samsung/stumpy/smihandler.c
@@ -36,16 +36,16 @@ void mainboard_smi_sleep(u8 slp_typ)
 	switch (slp_typ) {
 	case ACPI_S3:
 	case ACPI_S4:
-		it8772f_gpio_led(DUMMY_DEV, 4 /* set */, (0x1<<5) /* select */,
-			(0x1<<5) /* polarity */, (0x1<<5) /* 1=pullup */,
-			(0x1<<5) /* output */, 0x00, /* 0=Alternate function */
+		it8772f_gpio_led(DUMMY_DEV, 4 /* set */, (0x1 << 5) /* select */,
+			(0x1 << 5) /* polarity */, (0x1 << 5) /* 1 = pullup */,
+			(0x1 << 5) /* output */, 0x00, /* 0 = Alternate function */
 			SIO_GPIO_BLINK_GPIO45, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);
 		break;
 
 	case ACPI_S5:
-		it8772f_gpio_led(DUMMY_DEV, 4 /* set */, (0x1<<5) /* select */,
-			0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */,
-			(0x1<<5) /* output */, (0x1<<5) /* 1=Simple IO function */,
+		it8772f_gpio_led(DUMMY_DEV, 4 /* set */, (0x1 << 5) /* select */,
+			0x00 /* polarity: non-inverting */, 0x00 /* 0 = pulldown */,
+			(0x1 << 5) /* output */, (0x1 << 5) /* 1 = Simple IO function */,
 			SIO_GPIO_BLINK_GPIO45, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);
 		break;
 	default:
diff --git a/src/mainboard/siemens/mc_tcu3/romstage.c b/src/mainboard/siemens/mc_tcu3/romstage.c
index c8cc66b49e..15d949e2ec 100644
--- a/src/mainboard/siemens/mc_tcu3/romstage.c
+++ b/src/mainboard/siemens/mc_tcu3/romstage.c
@@ -145,7 +145,7 @@ const PCH_AZALIA_VERB_TABLE mAzaliaVerbTable[] = { {
 		0x10EC0262,     /* Vendor ID/Device IDA */
 		0x0000,         /* SubSystem ID */
 		0xFF,           /* Revision IDA */
-		0x01,           /* Front panel support (1=yes, 2=no) */
+		0x01,           /* Front panel support (1 = yes, 2 = no) */
 		0x000B,         /* Number of Rear Jacks = 11 */
 		0x0002          /* Number of Front Jacks = 2 */
 	},
diff --git a/src/mainboard/siemens/sitemp_g1p1/fadt.c b/src/mainboard/siemens/sitemp_g1p1/fadt.c
index 7d7221d275..360a427c21 100644
--- a/src/mainboard/siemens/sitemp_g1p1/fadt.c
+++ b/src/mainboard/siemens/sitemp_g1p1/fadt.c
@@ -57,7 +57,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 
 	fadt->firmware_ctrl = (u32) facs;
 	fadt->dsdt = (u32) dsdt;
-	/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
+	/* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
 	fadt->preferred_pm_profile = 0x03;
 	fadt->sci_int = 9;
 	/* disable system management mode by setting to 0: */
@@ -86,11 +86,11 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF);
 	pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8);
 
-	pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses
+	pm_iowrite(0x0E, 1 << 3 | 0 << 2); /* AcpiDecodeEnable, When set, SB uses
 					* the contents of the PM registers at
 					* index 20-2B to decode ACPI I/O address.
 					* AcpiSmiEn & SmiCmdEn*/
-	pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
+	pm_iowrite(0x10, 1 << 1 | 1 << 3| 1 << 5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
 	outl(0x1, ACPI_PM1_CNT_BLK);		  /* set SCI_EN */
 
 	fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c
index 41811e4e87..8c65972f31 100644
--- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c
+++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c
@@ -657,7 +657,7 @@ static void update_subsystemid( device_t dev )
 		dev->subsystem_device = 0x4077; // U1P0 = 0x4077
 	}
 	printk(BIOS_INFO, "%s [%x/%x]\n", dev_name(dev), dev->subsystem_vendor, dev->subsystem_device );
-	for( i=0; slot[i].bus < 255; i++) {
+	for( i = 0; slot[i].bus < 255; i++) {
 		device_t d;
 		d = dev_find_slot(slot[i].bus,slot[i].devfn);
 		if( d ) {
diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c
index 634f974e48..a7f2c965d4 100644
--- a/src/mainboard/siemens/sitemp_g1p1/romstage.c
+++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c
@@ -141,7 +141,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	if( (cpuid1.edx & 0x6) == 0x6 ) {
 
 		/* Read FIDVID_STATUS */
-		msr=rdmsr(0xc0010042);
+		msr = rdmsr(0xc0010042);
 		__DEBUG__("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 
 		enable_fid_change();
@@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		init_fidvid_bsp(bsp_apicid);
 
 		/* show final fid and vid */
-		msr=rdmsr(0xc0010042);
+		msr = rdmsr(0xc0010042);
 		__DEBUG__("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 
 	} else {
diff --git a/src/mainboard/sunw/ultra40/mptable.c b/src/mainboard/sunw/ultra40/mptable.c
index eeae519b20..d4fdfc11b7 100644
--- a/src/mainboard/sunw/ultra40/mptable.c
+++ b/src/mainboard/sunw/ultra40/mptable.c
@@ -139,50 +139,50 @@ static void *smp_write_config_table(void *v)
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +0x0a)<<2)|0, apicid_ck804, 0x15); // 21
 
 //Slot 1 PCIE x16
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
+        for(i = 0; i < 4; i++) {
+                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00 << 2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
         }
 
 //Onboard Firewire
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05<<2)|0, apicid_ck804, 0x13); // 19
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05 << 2)|0, apicid_ck804, 0x13); // 19
 
 //Slot 2 PCI 32
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4);
+        for(i = 0; i < 4; i++) {
+                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04 << 2)|i, apicid_ck804, 0x10 + (0+i)%4);
         }
 
 	if(pci1234[2] & 0xf) {
 //Onboard ck804b NIC
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21=53
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21 = 53
 
 //Slot 3 PCIE x16
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|i, apicid_ck804b, 0x10 + (2+i+4-sbdnb%4)%4);
+        for(i = 0; i < 4; i++) {
+                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00 << 2)|i, apicid_ck804b, 0x10 + (2+i+4-sbdnb%4)%4);
         }
 	}
 
 //Channel B of 8131
 
 //Slot 4 PCI-X 100/66
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (0+i)%4);
+        for(i = 0; i < 4; i++) {
+                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4 << 2)|i, apicid_8131_2, (0+i)%4);
         }
 
 //Slot 5 PCIX 100/66
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (1+i)%4); // 29
+        for(i = 0; i < 4; i++) {
+                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9 << 2)|i, apicid_8131_2, (1+i)%4); // 29
         }
 
 //OnBoard LSI SCSI
-        for(i=0;i<2;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|i, apicid_8131_2, (2+i)%4); //30
+        for(i = 0; i < 2; i++) {
+                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6 << 2)|i, apicid_8131_2, (2+i)%4); //30
         }
 
 //Channel A of 8131
 
 //Slot 6 PCIX 133/100/66
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|i, apicid_8131_1, (0+i)%4); //24
+        for(i = 0; i < 4; i++) {
+                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4 << 2)|i, apicid_8131_1, (0+i)%4); //24
         }
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c
index ecb7fe7c32..d0f569c355 100644
--- a/src/mainboard/sunw/ultra40/romstage.c
+++ b/src/mainboard/sunw/ultra40/romstage.c
@@ -33,9 +33,9 @@ static void sio_gpio_setup(void)
         unsigned value;
 
         /*Enable onboard scsi*/
-        lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
+        lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1 << 7)|(0 << 2)|(0 << 1)|(0 << 0)); // GP21, offset 0x2c, DISABLE_SCSI_L
         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
-        lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
+        lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1 << 1)));
 }
 #endif
 
@@ -55,12 +55,12 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 //set GPIO to input mode
 #define CK804_MB_SETUP \
-                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
-                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
-                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
-                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
-                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
-                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
+                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
+                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
+                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
+                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
+                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
+                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
 
 #include "southbridge/nvidia/ck804/early_setup_car.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
@@ -79,7 +79,7 @@ static void sio_setup(void)
         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
 
         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
-        dword |= (1<<29)|(1<<0);
+        dword |= (1 << 29)|(1 << 0);
         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
 
         lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
diff --git a/src/mainboard/sunw/ultra40m2/mptable.c b/src/mainboard/sunw/ultra40m2/mptable.c
index 89bb9ebd89..0493d38877 100644
--- a/src/mainboard/sunw/ultra40m2/mptable.c
+++ b/src/mainboard/sunw/ultra40m2/mptable.c
@@ -58,8 +58,8 @@ static void *smp_write_config_table(void *v)
 
 		/* Initialize interrupt mapping*/
 			dword = pci_read_config32(dev, 0x74);
-			dword &= ~(1<<15);
-			dword |= 1<<2;
+			dword &= ~(1 << 15);
+			dword |= 1 << 2;
 			pci_write_config32(dev, 0x74, dword);
 
 			dword = 0x43c6c643;
diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c
index 7a5ce93319..a7489daa6b 100644
--- a/src/mainboard/sunw/ultra40m2/romstage.c
+++ b/src/mainboard/sunw/ultra40m2/romstage.c
@@ -78,11 +78,11 @@ static void sio_setup(void)
 	pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
 
 	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
-	dword |= (1<<0);
+	dword |= (1 << 0);
 	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 
 	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
-	dword |= (1<<16);
+	dword |= (1 << 16);
 	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
 }
 
@@ -142,7 +142,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #if CONFIG_SET_FIDVID
 	{
 		msr_t msr;
-		msr=rdmsr(0xc0010042);
+		msr = rdmsr(0xc0010042);
 		printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
 	}
 	enable_fid_change();
@@ -151,7 +151,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	// show final fid and vid
 	{
 		msr_t msr;
-		msr=rdmsr(0xc0010042);
+		msr = rdmsr(0xc0010042);
 		printk(BIOS_DEBUG, "end   msr fid, vid %08x%08x\n", msr.hi, msr.lo);
 	}
 #endif
diff --git a/src/mainboard/supermicro/h8dme/mptable.c b/src/mainboard/supermicro/h8dme/mptable.c
index bf8f0da640..a76cf1bd65 100644
--- a/src/mainboard/supermicro/h8dme/mptable.c
+++ b/src/mainboard/supermicro/h8dme/mptable.c
@@ -91,25 +91,25 @@ static void *smp_write_config_table(void *v)
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+8)<<2)|0, apicid_mcp55, 0x16); // 22
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+9)<<2)|0, apicid_mcp55, 0x15); // 21
 
-	for(j=7; j>=2; j--) {
+	for(j = 7; j >= 2; j--) {
 		if(!bus_mcp55[j]) continue;
-	        for(i=0;i<4;i++) {
-        	        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00<<2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
+	        for(i = 0; i < 4; i++) {
+        	        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00 << 2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
         	}
 	}
 
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], (0x04<<2)|i, apicid_mcp55, 0x10 + (0+i)%4);
+        for(i = 0; i < 4; i++) {
+                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], (0x04 << 2)|i, apicid_mcp55, 0x10 + (0+i)%4);
         }
 
 
 	if(bus_pcix[0]) {
-		for(i=0;i<2;i++) {
-			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4<<2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17
+		for(i = 0; i < 2; i++) {
+			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4 << 2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17
 		}
 
-		for(i=0;i<4;i++) {
-			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[1], (4<<2)|i, apicid_mcp55, 0x10 + (2+i+4-sbdn%4)%4); // 18, 19, 16, 17
+		for(i = 0; i < 4; i++) {
+			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[1], (4 << 2)|i, apicid_mcp55, 0x10 + (2+i+4-sbdn%4)%4); // 18, 19, 16, 17
 		}
 	}
 
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index aeff991355..d85ae5ba68 100644
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -77,7 +77,7 @@ static void sio_setup(void)
 	uint8_t byte;
 
 	enable_smbus();
-//      smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
+//      smbusx_write_byte(1, (0x58 >> 1), 0, 0x80); /* select bank0 */
 	smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff);	/* set FAN ctrl to DC mode */
 
 	byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b);
@@ -94,8 +94,8 @@ static void sio_setup(void)
 }
 
 /* We have no idea where the SMBUS switch is. This doesn't do anything ATM. */
-#define RC0 (2<<8)
-#define RC1 (1<<8)
+#define RC0 (2 << 8)
+#define RC1 (1 << 8)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
diff --git a/src/mainboard/supermicro/h8dmr/mptable.c b/src/mainboard/supermicro/h8dmr/mptable.c
index eda7dc6983..7ca1091855 100644
--- a/src/mainboard/supermicro/h8dmr/mptable.c
+++ b/src/mainboard/supermicro/h8dmr/mptable.c
@@ -92,25 +92,25 @@ static void *smp_write_config_table(void *v)
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+8)<<2)|0, apicid_mcp55, 0x16); // 22
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+9)<<2)|0, apicid_mcp55, 0x15); // 21
 
-	for(j=7; j>=2; j--) {
+	for(j = 7; j >= 2; j--) {
 		if(!bus_mcp55[j]) continue;
-	        for(i=0;i<4;i++) {
-        	        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00<<2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
+	        for(i = 0; i < 4; i++) {
+        	        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00 << 2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
         	}
 	}
 
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], (0x04<<2)|i, apicid_mcp55, 0x10 + (0+i)%4);
+        for(i = 0; i < 4; i++) {
+                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], (0x04 << 2)|i, apicid_mcp55, 0x10 + (0+i)%4);
         }
 
 
 	if(bus_pcix[0]) {
-		for(i=0;i<2;i++) {
-			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4<<2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17
+		for(i = 0; i < 2; i++) {
+			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4 << 2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17
 		}
 
-		for(i=0;i<4;i++) {
-			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[1], (4<<2)|i, apicid_mcp55, 0x10 + (2+i+4-sbdn%4)%4); // 18, 19, 16, 17
+		for(i = 0; i < 4; i++) {
+			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[1], (4 << 2)|i, apicid_mcp55, 0x10 + (2+i+4-sbdn%4)%4); // 18, 19, 16, 17
 		}
 	}
 
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index eb7381724e..b137b6b76e 100644
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -69,19 +69,19 @@ static void sio_setup(void)
         uint8_t byte;
 
         enable_smbus();
-//	smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
-	smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
+//	smbusx_write_byte(1, (0x58 >> 1), 0, 0x80); /* select bank0 */
+	smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
 
         byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
         byte |= 0x20;
         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
 
         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
-        dword |= (1<<0);
+        dword |= (1 << 0);
         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 
         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
-        dword |= (1<<16);
+        dword |= (1 << 16);
         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
 }
 
@@ -144,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #if CONFIG_SET_FIDVID
         {
                 msr_t msr;
-                msr=rdmsr(0xc0010042);
+                msr = rdmsr(0xc0010042);
                 printk(BIOS_DEBUG, "begin msr fid, vid %08x, %08x\n", msr.hi, msr.lo);
         }
         enable_fid_change();
@@ -153,7 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         // show final fid and vid
         {
                 msr_t msr;
-                msr=rdmsr(0xc0010042);
+                msr = rdmsr(0xc0010042);
                 printk(BIOS_DEBUG, "end   msr fid, vid %08x, %08x\n", msr.hi, msr.lo);
         }
 #endif
diff --git a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
index 673910562e..8a0a6ec51f 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
@@ -69,7 +69,7 @@ void get_bus_conf(void)
 	device_t dev;
 	int i;
 
-	if(get_bus_conf_done==1) return; //do it only once
+	if(get_bus_conf_done == 1) return; //do it only once
 
 	get_bus_conf_done = 1;
 
@@ -79,7 +79,7 @@ void get_bus_conf(void)
 	memset(m, 0, sizeof(struct mb_sysconf_t));
 
 	sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
-	for(i=0;i<sysconf.hc_possible_num; i++) {
+	for(i = 0; i < sysconf.hc_possible_num; i++) {
 		sysconf.pci1234[i] = pci1234x[i];
 		sysconf.hcdn[i] = hcdnx[i];
 	}
@@ -98,7 +98,7 @@ void get_bus_conf(void)
 			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
 		}
 
-		for(i=2; i<8;i++) {
+		for(i = 2; i < 8; i++) {
 			dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
 			if (dev) {
 				m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
diff --git a/src/mainboard/supermicro/h8dmr_fam10/mptable.c b/src/mainboard/supermicro/h8dmr_fam10/mptable.c
index e1ca607888..631ff7d488 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/mptable.c
@@ -88,15 +88,15 @@ static void *smp_write_config_table(void *v)
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
 
-	for(j=7; j>=2; j--) {
+	for(j = 7; j >= 2; j--) {
 		if(!m->bus_mcp55[j]) continue;
-		for(i=0;i<4;i++) {
-			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
+		for(i = 0; i < 4; i++) {
+			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00 << 2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
 		}
 	}
 
-	for(j=0; j<1; j++)
-		for(i=0;i<4;i++) {
+	for(j = 0; j < 1; j++)
+		for(i = 0; i < 4; i++) {
 			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
 		}
 
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 7be3209ecb..7766f3a5bf 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -71,7 +71,7 @@ static void sio_setup(void)
 	uint8_t byte;
 
 	enable_smbus();
-	// smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
+	// smbusx_write_byte(1, (0x58 >> 1), 0, 0x80); /* select bank0 */
 	/* set FAN ctrl to DC mode */
 	smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff);
 
diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c
index c56833420e..ac978a1ea7 100644
--- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c
+++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c
@@ -53,7 +53,7 @@ static UINT8 select_socket(UINT8 socket_id)
 	gpio56_to_53 = pci_read_config8(sm_dev, PCI_REG_GPIO_56_to_53_CNTRL);
 	value  = gpio56_to_53 & (~GPIO_OUT_BIT_GPIO54_to_53_MASK);
 	value |= socket_id;
-	value &= (~GPIO_OUT_ENABLE_BIT_GPIO54_to_53_MASK); // 0=Output Enabled, 1=Tristate
+	value &= (~GPIO_OUT_ENABLE_BIT_GPIO54_to_53_MASK); // 0 = Output Enabled, 1 = Tristate
 	pci_write_config8(sm_dev, PCI_REG_GPIO_56_to_53_CNTRL, value);
 
 	return gpio56_to_53;
diff --git a/src/mainboard/supermicro/h8qgi/fadt.c b/src/mainboard/supermicro/h8qgi/fadt.c
index f4fe61e0e9..ae6991f56c 100644
--- a/src/mainboard/supermicro/h8qgi/fadt.c
+++ b/src/mainboard/supermicro/h8qgi/fadt.c
@@ -55,7 +55,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	else
 		fadt->dsdt = (uintptr_t)dsdt;
 
-	/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
+	/* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
 	fadt->preferred_pm_profile = 0x03;
 	fadt->sci_int = 9;
 	/* disable system management mode by setting to 0: */
diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c
index 68af428e48..7af085d19e 100644
--- a/src/mainboard/supermicro/h8qgi/mptable.c
+++ b/src/mainboard/supermicro/h8qgi/mptable.c
@@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v)
 		dword = pci_read_config32(dev, 0xAC);
 		dword = dword & ~(7 << 26);
 		dword = dword | (6 << 26); /* 0: INTA, ...., 7: INTH */
-		/* dword |= 1<<22; PIC and APIC co exists */
+		/* dword |= 1 << 22; PIC and APIC co exists */
 		pci_write_config32(dev, 0xAC, dword);
 #endif
 
diff --git a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
index 5a7157bcbe..813fa77ea2 100644
--- a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
@@ -71,7 +71,7 @@ void get_bus_conf(void)
 	device_t dev;
 	int i;
 
-	if(get_bus_conf_done==1) return; //do it only once
+	if(get_bus_conf_done == 1) return; //do it only once
 
 	get_bus_conf_done = 1;
 
@@ -81,7 +81,7 @@ void get_bus_conf(void)
 	memset(m, 0, sizeof(struct mb_sysconf_t));
 
 	sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
-	for(i=0;i<sysconf.hc_possible_num; i++) {
+	for(i = 0; i < sysconf.hc_possible_num; i++) {
 		sysconf.pci1234[i] = pci1234x[i];
 		sysconf.hcdn[i] = hcdnx[i];
 	}
@@ -104,7 +104,7 @@ void get_bus_conf(void)
 			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
 		}
 
-		for(i=2; i<8;i++) {
+		for(i = 2; i < 8; i++) {
 			dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
 			if (dev) {
 				m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c
index e4dd3a8c09..9a60194b7c 100644
--- a/src/mainboard/supermicro/h8qme_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8qme_fam10/mptable.c
@@ -86,15 +86,15 @@ static void *smp_write_config_table(void *v)
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|0, m->apicid_mcp55, 0x5); /* 5  eth0, OK*/
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|1, m->apicid_mcp55, 0xb); /* 11 eth1, OK*/
 
-	for(j=7;j>=2; j--) {
+	for(j = 7;j >= 2; j--) {
 		if(!m->bus_mcp55[j]) continue;
-		for(i=0;i<4;i++) {
-			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
+		for(i = 0; i < 4; i++) {
+			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00 << 2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
 		}
 	}
 
-	for(j=0; j<1; j++)
-		for(i=0;i<4;i++) {
+	for(j = 0; j < 1; j++)
+		for(i = 0; i < 4; i++) {
 			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
 		}
 
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 4661f458f0..f82ddd13c2 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -77,19 +77,19 @@ static void sio_setup(void)
 	uint32_t dword;
 	uint8_t byte;
 	enable_smbus();
-//	smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
-	smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
+//	smbusx_write_byte(1, (0x58 >> 1), 0, 0x80); /* select bank0 */
+	smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
 
 	byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
 	byte |= 0x20;
 	pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
 
 	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
-	dword |= (1<<0);
+	dword |= (1 << 0);
 	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 
 	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
-	dword |= (1<<16);
+	dword |= (1 << 16);
 	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
 }
 
@@ -260,7 +260,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x3A);
 
 	/* show final fid and vid */
-	msr=rdmsr(0xc0010071);
+	msr = rdmsr(0xc0010071);
 	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 #endif
 
diff --git a/src/mainboard/supermicro/h8scm/fadt.c b/src/mainboard/supermicro/h8scm/fadt.c
index 330dc544a1..fda488f7fe 100644
--- a/src/mainboard/supermicro/h8scm/fadt.c
+++ b/src/mainboard/supermicro/h8scm/fadt.c
@@ -55,7 +55,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	else
 		fadt->dsdt = (uintptr_t)dsdt;
 
-	/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
+	/* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
 	fadt->preferred_pm_profile = 0x03;
 	fadt->sci_int = 9;
 	/* disable system management mode by setting to 0: */
diff --git a/src/mainboard/supermicro/h8scm/mptable.c b/src/mainboard/supermicro/h8scm/mptable.c
index 5b809c3b21..5ef7f3d8c0 100644
--- a/src/mainboard/supermicro/h8scm/mptable.c
+++ b/src/mainboard/supermicro/h8scm/mptable.c
@@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v)
 		dword = (u32 *)pci_read_config32(dev, 0xAC);
 		dword = dword & ~(7 << 26);
 		dword = dword | (6 << 26); /* 0: INTA, ...., 7: INTH */
-		/* dword |= 1<<22; PIC and APIC co exists */
+		/* dword |= 1 << 22; PIC and APIC co exists */
 		pci_write_config32(dev, 0xAC, dword);
 #endif
 
diff --git a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c b/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c
index 08910cc4c2..b50410a1b8 100644
--- a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c
+++ b/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c
@@ -29,7 +29,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 {
 	device_t dev;
 	u32 dword;
-	u32 gsi_base=0;
+	u32 gsi_base = 0;
 	/* create all subtables for processors */
 	current = acpi_create_madt_lapics(current);
 
diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c
index 9ae9476870..75a4544287 100644
--- a/src/mainboard/supermicro/h8scm_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8scm_fam10/mptable.c
@@ -72,7 +72,7 @@ static void *smp_write_config_table(void *v)
 			dword = (u32 *)((pci_read_config32(dev, 0xac) &
 					 ~(7 << 26)) | (6 << 26));
 
-			/* dword |= 1<<22; PIC and APIC co exists */
+			/* dword |= 1 << 22; PIC and APIC co exists */
 			pci_write_config32(dev, 0xac, (u32)dword);
 
 			/*
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index 7312683fc0..f2c79b4db1 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -188,7 +188,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x3A);
 
 	/* show final fid and vid */
-	msr=rdmsr(0xc0010071);
+	msr = rdmsr(0xc0010071);
 	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 #endif
 
diff --git a/src/mainboard/technexion/tim5690/fadt.c b/src/mainboard/technexion/tim5690/fadt.c
index f9768b20bd..b397f52aea 100644
--- a/src/mainboard/technexion/tim5690/fadt.c
+++ b/src/mainboard/technexion/tim5690/fadt.c
@@ -56,7 +56,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 
 	fadt->firmware_ctrl = (u32) facs;
 	fadt->dsdt = (u32) dsdt;
-	/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
+	/* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
 	fadt->preferred_pm_profile = 0x03;
 	fadt->sci_int = 9;
 	/* disable system management mode by setting to 0: */
@@ -85,11 +85,11 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF);
 	pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8);
 
-	pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses
+	pm_iowrite(0x0E, 1 << 3 | 0 << 2); /* AcpiDecodeEnable, When set, SB uses
 					* the contents of the PM registers at
 					* index 20-2B to decode ACPI I/O address.
 					* AcpiSmiEn & SmiCmdEn*/
-	pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
+	pm_iowrite(0x10, 1 << 1 | 1 << 3| 1 << 5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
 	outl(0x1, ACPI_PM1_CNT_BLK);		  /* set SCI_EN */
 
 	fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
diff --git a/src/mainboard/technexion/tim5690/mptable.c b/src/mainboard/technexion/tim5690/mptable.c
index 39192b071c..8895163651 100644
--- a/src/mainboard/technexion/tim5690/mptable.c
+++ b/src/mainboard/technexion/tim5690/mptable.c
@@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v)
 			dword = pci_read_config32(dev, 0xac);
 			dword &= ~(7 << 26);
 			dword |= 6 << 26;	/* 0: INTA, ...., 7: INTH */
-			/* dword |= 1<<22; PIC and APIC co exists */
+			/* dword |= 1 << 22; PIC and APIC co exists */
 			pci_write_config32(dev, 0xac, dword);
 
 			/*
diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c
index b94b06c416..e534617e4d 100644
--- a/src/mainboard/technexion/tim5690/romstage.c
+++ b/src/mainboard/technexion/tim5690/romstage.c
@@ -116,7 +116,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	cpuid1 = cpuid(0x80000007);
 	if ((cpuid1.edx & 0x6) == 0x6) {
 		/* Read FIDVID_STATUS */
-		msr=rdmsr(0xc0010042);
+		msr = rdmsr(0xc0010042);
 		printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 
 		enable_fid_change();
@@ -124,7 +124,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		init_fidvid_bsp(bsp_apicid);
 
 		/* show final fid and vid */
-		msr=rdmsr(0xc0010042);
+		msr = rdmsr(0xc0010042);
 		printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 	} else {
 		printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
diff --git a/src/mainboard/technexion/tim5690/tn_post_code.c b/src/mainboard/technexion/tim5690/tn_post_code.c
index 1fa49355a4..213034a316 100644
--- a/src/mainboard/technexion/tim5690/tn_post_code.c
+++ b/src/mainboard/technexion/tim5690/tn_post_code.c
@@ -36,7 +36,7 @@
 void technexion_post_code_init(void)
 {
    uint8_t reg8_data;
-   device_t dev=0;
+   device_t dev = 0;
 
    // SMBus Module and ACPI Block (Device 20, Function 0)
    dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_SM), 0);
@@ -44,80 +44,80 @@ void technexion_post_code_init(void)
    // LED[bit0]:GPIO0
    // This is reference SB600 RRG 4.1.1 GPIO
    reg8_data = pmio_read(0x60);
-   reg8_data |= (1<<7);  // 1: GPIO if not used by SATA
+   reg8_data |= (1 << 7);  // 1: GPIO if not used by SATA
    pmio_write(0x60, reg8_data);
 
    reg8_data = pci_read_config8(dev, 0x80);
-   reg8_data = ((reg8_data | (1<<0)) & ~(1<<4));
+   reg8_data = ((reg8_data | (1 << 0)) & ~(1 << 4));
    pci_write_config8(dev, 0x80, reg8_data);
 
    // LED[bit1]:GPIO1
    // This is reference SB600 RRG 4.1.1 GPIO
    reg8_data = pci_read_config8(dev, 0x80);
-   reg8_data = ((reg8_data | (1<<1)) & ~(1<<5));
+   reg8_data = ((reg8_data | (1 << 1)) & ~(1 << 5));
    pci_write_config8(dev, 0x80, reg8_data);
 
    // LED[bit2]:GPIO4
    // This is reference SB600 RRG 4.1.1 GPIO
    reg8_data = pmio_read(0x5e);
-   reg8_data &= ~(1<<7); // 0: GPIO if not used by SATA
+   reg8_data &= ~(1 << 7); // 0: GPIO if not used by SATA
    pmio_write(0x5e, reg8_data);
 
    reg8_data = pci_read_config8(dev, 0xa8);
-   reg8_data |= (1<<0);
+   reg8_data |= (1 << 0);
    pci_write_config8(dev, 0xa8, reg8_data);
 
    reg8_data = pci_read_config8(dev, 0xa9);
-   reg8_data &= ~(1<<0);
+   reg8_data &= ~(1 << 0);
    pci_write_config8(dev, 0xa9, reg8_data);
 
    // LED[bit3]:GPIO6
    // This is reference SB600 RRG 4.1.1 GPIO
    reg8_data = pmio_read(0x60);
-   reg8_data |= (1<<7); // 1: GPIO if not used by SATA
+   reg8_data |= (1 << 7); // 1: GPIO if not used by SATA
    pmio_write(0x60, reg8_data);
 
    reg8_data = pci_read_config8(dev, 0xa8);
-   reg8_data |= (1<<2);
+   reg8_data |= (1 << 2);
    pci_write_config8(dev, 0xa8, reg8_data);
 
    reg8_data = pci_read_config8(dev, 0xa9);
-   reg8_data &= ~(1<<2);
+   reg8_data &= ~(1 << 2);
    pci_write_config8(dev, 0xa9, reg8_data);
    // LED[bit4]:GPIO7
    // This is reference SB600 RRG 4.1.1 GPIO
    reg8_data = pci_read_config8(dev, 0xa8);
-   reg8_data |= (1<<3);
+   reg8_data |= (1 << 3);
    pci_write_config8(dev, 0xa8, reg8_data);
 
    reg8_data = pci_read_config8(dev, 0xa9);
-   reg8_data &= ~(1<<3);
+   reg8_data &= ~(1 << 3);
    pci_write_config8(dev, 0xa9, reg8_data);
 
    // LED[bit5]:GPIO8
    // This is reference SB600 RRG 4.1.1 GPIO
    reg8_data = pci_read_config8(dev, 0xa8);
-   reg8_data |= (1<<4);
+   reg8_data |= (1 << 4);
    pci_write_config8(dev, 0xa8, reg8_data);
 
    reg8_data = pci_read_config8(dev, 0xa9);
-   reg8_data &= ~(1<<4);
+   reg8_data &= ~(1 << 4);
    pci_write_config8(dev, 0xa9, reg8_data);
 
    // LED[bit6]:GPIO10
    // This is reference SB600 RRG 4.1.1 GPIO
    reg8_data = pci_read_config8(dev, 0xab);
-   reg8_data = ((reg8_data | (1<<0)) & ~(1<<1));
+   reg8_data = ((reg8_data | (1 << 0)) & ~(1 << 1));
    pci_write_config8(dev, 0xab, reg8_data);
 
    // LED[bit7]:GPIO66
    // This is reference SB600 RRG 4.1.1 GPIO
    reg8_data = pmio_read(0x68);
-   reg8_data &= ~(1<<5); // 0: GPIO
+   reg8_data &= ~(1 << 5); // 0: GPIO
    pmio_write(0x68, reg8_data);
 
    reg8_data = pci_read_config8(dev, 0x7e);
-   reg8_data = ((reg8_data | (1<<1)) & ~(1<<5));
+   reg8_data = ((reg8_data | (1 << 1)) & ~(1 << 5));
    pci_write_config8(dev, 0x7e, reg8_data);
 
 }
@@ -129,7 +129,7 @@ void technexion_post_code_init(void)
 void technexion_post_code(uint8_t udata8)
 {
    uint8_t u8_data;
-   device_t dev=0;
+   device_t dev = 0;
 
    // SMBus Module and ACPI Block (Device 20, Function 0)
 #ifdef __PRE_RAM__
@@ -143,80 +143,80 @@ void technexion_post_code(uint8_t udata8)
    // LED[bit0]:GPIO0
    u8_data = pci_read_config8(dev, 0x80);
    if (udata8 & 0x1) {
-      u8_data |= (1<<0);
+      u8_data |= (1 << 0);
    }
    else {
-      u8_data &= ~(1<<0);
+      u8_data &= ~(1 << 0);
    }
    pci_write_config8(dev, 0x80, u8_data);
 
    // LED[bit1]:GPIO1
    u8_data = pci_read_config8(dev, 0x80);
    if (udata8 & 0x2) {
-      u8_data |= (1<<1);
+      u8_data |= (1 << 1);
    }
    else {
-      u8_data &= ~(1<<1);
+      u8_data &= ~(1 << 1);
    }
    pci_write_config8(dev, 0x80, u8_data);
 
    // LED[bit2]:GPIO4
    u8_data = pci_read_config8(dev, 0xa8);
    if (udata8 & 0x4) {
-      u8_data |= (1<<0);
+      u8_data |= (1 << 0);
    }
    else {
-      u8_data &= ~(1<<0);
+      u8_data &= ~(1 << 0);
    }
    pci_write_config8(dev, 0xa8, u8_data);
 
    // LED[bit3]:GPIO6
    u8_data = pci_read_config8(dev, 0xa8);
    if (udata8 & 0x8) {
-      u8_data |= (1<<2);
+      u8_data |= (1 << 2);
    }
    else {
-      u8_data &= ~(1<<2);
+      u8_data &= ~(1 << 2);
    }
    pci_write_config8(dev, 0xa8, u8_data);
 
    // LED[bit4]:GPIO7
    u8_data = pci_read_config8(dev, 0xa8);
    if (udata8 & 0x10) {
-      u8_data |= (1<<3);
+      u8_data |= (1 << 3);
    }
    else {
-      u8_data &= ~(1<<3);
+      u8_data &= ~(1 << 3);
    }
    pci_write_config8(dev, 0xa8, u8_data);
 
    // LED[bit5]:GPIO8
    u8_data = pci_read_config8(dev, 0xa8);
    if (udata8 & 0x20) {
-      u8_data |= (1<<4);
+      u8_data |= (1 << 4);
    }
    else {
-      u8_data &= ~(1<<4);
+      u8_data &= ~(1 << 4);
    }
    pci_write_config8(dev, 0xa8, u8_data);
 
    // LED[bit6]:GPIO10
    u8_data = pci_read_config8(dev, 0xab);
    if (udata8 & 0x40) {
-      u8_data |= (1<<0);
+      u8_data |= (1 << 0);
    }
    else {
-      u8_data &= ~(1<<0);
+      u8_data &= ~(1 << 0);
    }
    pci_write_config8(dev, 0xab, u8_data);
 
    // LED[bit7]:GPIO66
    u8_data = pci_read_config8(dev, 0x7e);
    if (udata8 & 0x80) {
-      u8_data |= (1<<1);
+      u8_data |= (1 << 1);
    }
    else {
-      u8_data &= ~(1<<1);
+      u8_data &= ~(1 << 1);
    }
    pci_write_config8(dev, 0x7e, u8_data);
 
diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c
index 939becfa78..9e1c58d29e 100644
--- a/src/mainboard/technexion/tim8690/mainboard.c
+++ b/src/mainboard/technexion/tim8690/mainboard.c
@@ -59,7 +59,7 @@ static void enable_onboard_nic(void)
 	byte |= ( 1 << 7);
 	pci_write_config8(sm_dev, 0x9a, byte);
 
-	byte=pm_ioread(0x59);
+	byte = pm_ioread(0x59);
 	byte &= ~( 1<< 5);
 	pm_iowrite(0x59,byte);
 
diff --git a/src/mainboard/technexion/tim8690/mptable.c b/src/mainboard/technexion/tim8690/mptable.c
index 39192b071c..8895163651 100644
--- a/src/mainboard/technexion/tim8690/mptable.c
+++ b/src/mainboard/technexion/tim8690/mptable.c
@@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v)
 			dword = pci_read_config32(dev, 0xac);
 			dword &= ~(7 << 26);
 			dword |= 6 << 26;	/* 0: INTA, ...., 7: INTH */
-			/* dword |= 1<<22; PIC and APIC co exists */
+			/* dword |= 1 << 22; PIC and APIC co exists */
 			pci_write_config32(dev, 0xac, dword);
 
 			/*
diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c
index e052d923a5..b1805a9d8f 100644
--- a/src/mainboard/technexion/tim8690/romstage.c
+++ b/src/mainboard/technexion/tim8690/romstage.c
@@ -111,7 +111,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	cpuid1 = cpuid(0x80000007);
 	if ((cpuid1.edx & 0x6) == 0x6 ) {
 		/* Read FIDVID_STATUS */
-		msr=rdmsr(0xc0010042);
+		msr = rdmsr(0xc0010042);
 		printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 
 		enable_fid_change();
@@ -119,7 +119,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		init_fidvid_bsp(bsp_apicid);
 
 		/* show final fid and vid */
-		msr=rdmsr(0xc0010042);
+		msr = rdmsr(0xc0010042);
 		printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 	} else {
 		printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
diff --git a/src/mainboard/thomson/ip1000/irq_tables.c b/src/mainboard/thomson/ip1000/irq_tables.c
index e8ef598ae3..e99adfcbc5 100644
--- a/src/mainboard/thomson/ip1000/irq_tables.c
+++ b/src/mainboard/thomson/ip1000/irq_tables.c
@@ -21,7 +21,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_VERSION,    /* u16 version   */
 	32+16*CONFIG_IRQ_SLOT_COUNT,	 /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
 	0x00,		 /* Where the interrupt router lies (bus) */
-	(0x1f<<3)|0x0,   /* Where the interrupt router lies (dev) */
+	(0x1f << 3)|0x0,   /* Where the interrupt router lies (dev) */
 	0,		 /* IRQs devoted exclusively to PCI usage */
 	0x8086,		 /* Vendor */
 	0x24c0,		 /* Device */
@@ -29,14 +29,14 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
 	0x07,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
 	{
-		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x02<<3)|0x0, {{0x60, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IGD VGA */
-		{0x00,(0x1d<<3)|0x0, {{0x60, 0x0ef8}, {0x63, 0x0ef8}, {0x62, 0x0ef8}, {0x6b, 0x00ef8}}, 0x0, 0x0}, /* [A] USB1, [B] USB2, [C] USB3, [D] EHCI */
-		{0x00,(0x1f<<3)|0x0, {{0x62, 0x0ef8}, {0x61, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IDE, [B] SMBUS, [B] AUDIO, [B] MODEM */
-		{0x01,(0x08<<3)|0x0, {{0x68, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] ETHERNET */
-		{0x01,(0x00<<3)|0x0, {{0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x0ef8}, {0x63, 0x00ef8}}, 0x1, 0x0}, /* PCI SLOT 1 */
-		{0x01,(0x01<<3)|0x0, {{0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x00ef8}}, 0x2, 0x0}, /* PCI SLOT 2 */
-		{0x01,(0x02<<3)|0x0, {{0x62, 0x0ef8}, {0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x00ef8}}, 0x3, 0x0}, /* PCI SLOT 3 */
+		/* bus,       dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,(0x02 << 3)|0x0, {{0x60, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IGD VGA */
+		{0x00,(0x1d << 3)|0x0, {{0x60, 0x0ef8}, {0x63, 0x0ef8}, {0x62, 0x0ef8}, {0x6b, 0x00ef8}}, 0x0, 0x0}, /* [A] USB1, [B] USB2, [C] USB3, [D] EHCI */
+		{0x00,(0x1f << 3)|0x0, {{0x62, 0x0ef8}, {0x61, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IDE, [B] SMBUS, [B] AUDIO, [B] MODEM */
+		{0x01,(0x08 << 3)|0x0, {{0x68, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] ETHERNET */
+		{0x01,(0x00 << 3)|0x0, {{0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x0ef8}, {0x63, 0x00ef8}}, 0x1, 0x0}, /* PCI SLOT 1 */
+		{0x01,(0x01 << 3)|0x0, {{0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x00ef8}}, 0x2, 0x0}, /* PCI SLOT 2 */
+		{0x01,(0x02 << 3)|0x0, {{0x62, 0x0ef8}, {0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x00ef8}}, 0x3, 0x0}, /* PCI SLOT 3 */
 	}
 };
 
diff --git a/src/mainboard/thomson/ip1000/mainboard.c b/src/mainboard/thomson/ip1000/mainboard.c
index c387ac64d0..bdcc1fa00b 100644
--- a/src/mainboard/thomson/ip1000/mainboard.c
+++ b/src/mainboard/thomson/ip1000/mainboard.c
@@ -67,7 +67,7 @@ static void flash_gpios(void)
 	if ((manufacturer_id == 0x20) &&
 		((device_id == 0x2c) || (device_id == 0x2d))) {
 		printk(BIOS_DEBUG, "Detected ST M50FW0%c0 flash:\n",
-				(device_id==0x2c)?'4':'8');
+				(device_id == 0x2c)?'4':'8');
 		u8 fgpi = read8((u8 *)0xffbc0100);
 		printk(BIOS_DEBUG, "  FGPI0 [%c] FGPI1 [%c] FGPI2 [%c] FGPI3 [%c] FGPI4 [%c]\n",
 			(fgpi & (1 << 0)) ? 'X' : ' ',
diff --git a/src/mainboard/tyan/s2912/get_bus_conf.c b/src/mainboard/tyan/s2912/get_bus_conf.c
index 0bc852ed7a..d13f737aa1 100644
--- a/src/mainboard/tyan/s2912/get_bus_conf.c
+++ b/src/mainboard/tyan/s2912/get_bus_conf.c
@@ -67,7 +67,7 @@ void get_bus_conf(void)
 	device_t dev;
 	int i;
 
-	if(get_bus_conf_done==1) return; //do it only once
+	if(get_bus_conf_done == 1) return; //do it only once
 
 	get_bus_conf_done = 1;
 
@@ -77,7 +77,7 @@ void get_bus_conf(void)
 	memset(m, 0, sizeof(struct mb_sysconf_t));
 
 	sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
-	for(i=0;i<sysconf.hc_possible_num; i++) {
+	for(i = 0; i < sysconf.hc_possible_num; i++) {
 		sysconf.pci1234[i] = pci1234x[i];
 		sysconf.hcdn[i] = hcdnx[i];
 	}
@@ -96,7 +96,7 @@ void get_bus_conf(void)
 		printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
 	}
 
-	for(i=2; i<8;i++) {
+	for(i = 2; i < 8; i++) {
 		dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
 		if (dev) {
 			m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
diff --git a/src/mainboard/tyan/s2912/mptable.c b/src/mainboard/tyan/s2912/mptable.c
index c878160d0b..9b46ad68a2 100644
--- a/src/mainboard/tyan/s2912/mptable.c
+++ b/src/mainboard/tyan/s2912/mptable.c
@@ -86,15 +86,15 @@ static void *smp_write_config_table(void *v)
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
 
-	for(j=7; j>=2; j--) {
+	for(j = 7; j >= 2; j--) {
 		if(!m->bus_mcp55[j]) continue;
-		for(i=0;i<4;i++) {
-			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
+		for(i = 0; i < 4; i++) {
+			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00 << 2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
 		}
 	}
 
-	for(j=0; j<1; j++)
-		for(i=0;i<4;i++) {
+	for(j = 0; j < 1; j++)
+		for(i = 0; i < 4; i++) {
 			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
 		}
 
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index c80e2d6061..8c012727fb 100644
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -82,11 +82,11 @@ static void sio_setup(void)
 
 	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
 	/*serial 0 */
-	dword |= (1<<0);
+	dword |= (1 << 0);
 	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 
 	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
-	dword |= (1<<16);
+	dword |= (1 << 16);
 	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
 }
 
@@ -147,7 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #if CONFIG_SET_FIDVID
 	{
 		msr_t msr;
-		msr=rdmsr(0xc0010042);
+		msr = rdmsr(0xc0010042);
 		printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
 	}
 	enable_fid_change();
@@ -156,7 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	// show final fid and vid
 	{
 		msr_t msr;
-		msr=rdmsr(0xc0010042);
+		msr = rdmsr(0xc0010042);
 		printk(BIOS_DEBUG, "end   msr fid, vid %08x%08x\n", msr.hi, msr.lo);
 	}
 #endif
diff --git a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
index 9d633a317b..29ab03da2f 100644
--- a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
+++ b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
@@ -68,7 +68,7 @@ void get_bus_conf(void)
 	device_t dev;
 	int i;
 
-	if(get_bus_conf_done==1) return; //do it only once
+	if(get_bus_conf_done == 1) return; //do it only once
 
 	get_bus_conf_done = 1;
 
@@ -78,7 +78,7 @@ void get_bus_conf(void)
 	memset(m, 0, sizeof(struct mb_sysconf_t));
 
 	sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
-	for(i=0;i<sysconf.hc_possible_num; i++) {
+	for(i = 0; i < sysconf.hc_possible_num; i++) {
 		sysconf.pci1234[i] = pci1234x[i];
 		sysconf.hcdn[i] = hcdnx[i];
 	}
@@ -97,7 +97,7 @@ void get_bus_conf(void)
 			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
 		}
 
-		for(i=2; i<8;i++) {
+		for(i = 2; i < 8; i++) {
 			dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
 			if (dev) {
 				m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
diff --git a/src/mainboard/tyan/s2912_fam10/mptable.c b/src/mainboard/tyan/s2912_fam10/mptable.c
index 157b363e2c..87d06b83e2 100644
--- a/src/mainboard/tyan/s2912_fam10/mptable.c
+++ b/src/mainboard/tyan/s2912_fam10/mptable.c
@@ -86,15 +86,15 @@ static void *smp_write_config_table(void *v)
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
 
-	for(j=7; j>=2; j--) {
+	for(j = 7; j >= 2; j--) {
 		if(!m->bus_mcp55[j]) continue;
-		for(i=0;i<4;i++) {
-			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
+		for(i = 0; i < 4; i++) {
+			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00 << 2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
 		}
 	}
 
-	for(j=0; j<1; j++)
-		for(i=0;i<4;i++) {
+	for(j = 0; j < 1; j++)
+		for(i = 0; i < 4; i++) {
 			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
 		}
 
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index bd64cabf30..e095b7960e 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -84,11 +84,11 @@ static void sio_setup(void)
 
 	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
 	/*serial 0 */
-	dword |= (1<<0);
+	dword |= (1 << 0);
 	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 
 	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
-	dword |= (1<<16);
+	dword |= (1 << 16);
 	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
 }
 
@@ -195,7 +195,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x3A);
 
 	/* show final fid and vid */
-	msr=rdmsr(0xc0010071);
+	msr = rdmsr(0xc0010071);
 	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 #endif
 
diff --git a/src/mainboard/tyan/s8226/fadt.c b/src/mainboard/tyan/s8226/fadt.c
index 330dc544a1..fda488f7fe 100644
--- a/src/mainboard/tyan/s8226/fadt.c
+++ b/src/mainboard/tyan/s8226/fadt.c
@@ -55,7 +55,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	else
 		fadt->dsdt = (uintptr_t)dsdt;
 
-	/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
+	/* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
 	fadt->preferred_pm_profile = 0x03;
 	fadt->sci_int = 9;
 	/* disable system management mode by setting to 0: */
diff --git a/src/mainboard/tyan/s8226/mptable.c b/src/mainboard/tyan/s8226/mptable.c
index 68af428e48..7af085d19e 100644
--- a/src/mainboard/tyan/s8226/mptable.c
+++ b/src/mainboard/tyan/s8226/mptable.c
@@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v)
 		dword = pci_read_config32(dev, 0xAC);
 		dword = dword & ~(7 << 26);
 		dword = dword | (6 << 26); /* 0: INTA, ...., 7: INTH */
-		/* dword |= 1<<22; PIC and APIC co exists */
+		/* dword |= 1 << 22; PIC and APIC co exists */
 		pci_write_config32(dev, 0xAC, dword);
 #endif
 
diff --git a/src/mainboard/via/epia-cn/irq_tables.c b/src/mainboard/via/epia-cn/irq_tables.c
index 13c7b66dec..ee8d488f97 100644
--- a/src/mainboard/via/epia-cn/irq_tables.c
+++ b/src/mainboard/via/epia-cn/irq_tables.c
@@ -30,16 +30,16 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
 	0x66,			/* Checksum */
 	{
-		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x14<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
-		{0x00,(0x0d<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0x0deb8}}, 0x2, 0x0},
-		{0x00,(0x0e<<3)|0x0, {{0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x3, 0x0},
-		{0x00,(0x13<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x4, 0x0},
-		{0x00,(0x11<<3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0},
-		{0x00,(0x0f<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0},
-		{0x00,(0x01<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0},
-		{0x00,(0x10<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0},
-		{0x00,(0x12<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
+		/* bus,       dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,(0x14 << 3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
+		{0x00,(0x0d << 3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0x0deb8}}, 0x2, 0x0},
+		{0x00,(0x0e << 3)|0x0, {{0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x3, 0x0},
+		{0x00,(0x13 << 3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x4, 0x0},
+		{0x00,(0x11 << 3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0},
+		{0x00,(0x0f << 3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0},
+		{0x00,(0x01 << 3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0},
+		{0x00,(0x10 << 3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0},
+		{0x00,(0x12 << 3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
 	}
 };
 
diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c
index a28bf784a2..39dd3fc97c 100644
--- a/src/mainboard/via/epia-cn/romstage.c
+++ b/src/mainboard/via/epia-cn/romstage.c
@@ -46,7 +46,7 @@ static void enable_mainboard_devices(void)
 	if (dev == PCI_DEV_INVALID)
 		die("Southbridge not found!!!\n");
 
-	/* bit=0 means enable function (per CX700 datasheet)
+	/* bit = 0 means enable function (per CX700 datasheet)
 	 *   5 16.1 USB 2
 	 *   4 16.0 USB 1
 	 *   3 15.0 SATA and PATA
@@ -55,7 +55,7 @@ static void enable_mainboard_devices(void)
 	 */
 	pci_write_config8(dev, 0x50, 0x80);
 
-	/* bit=1 means enable internal function (per CX700 datasheet)
+	/* bit = 1 means enable internal function (per CX700 datasheet)
 	 *   3 Internal RTC
 	 *   2 Internal PS2 Mouse
 	 *   1 Internal KBC Configuration
diff --git a/src/mainboard/via/pc2500e/irq_tables.c b/src/mainboard/via/pc2500e/irq_tables.c
index 53a4d79c29..e514df4363 100644
--- a/src/mainboard/via/pc2500e/irq_tables.c
+++ b/src/mainboard/via/pc2500e/irq_tables.c
@@ -29,17 +29,17 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
 	0x3e,			/* Checksum */
 	{
-		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x08<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0},
-		{0x00,(0x09<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0},
-		{0x00,(0x0a<<3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0},
-		{0x00,(0x0b<<3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0},
-		{0x00,(0x0c<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0},
-		{0x00,(0x11<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
-		{0x00,(0x0f<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
-		{0x00,(0x01<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
-		{0x00,(0x10<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
-		{0x00,(0x12<<3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},
+		/* bus,       dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,(0x08 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0},
+		{0x00,(0x09 << 3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0},
+		{0x00,(0x0a << 3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0},
+		{0x00,(0x0b << 3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0},
+		{0x00,(0x0c << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0},
+		{0x00,(0x11 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
+		{0x00,(0x0f << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
+		{0x00,(0x01 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
+		{0x00,(0x10 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
+		{0x00,(0x12 << 3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},
 	}
 };
 
diff --git a/src/mainboard/winent/mb6047/mptable.c b/src/mainboard/winent/mb6047/mptable.c
index 1a5685f7cd..3d9ffb5415 100644
--- a/src/mainboard/winent/mb6047/mptable.c
+++ b/src/mainboard/winent/mb6047/mptable.c
@@ -77,17 +77,17 @@ static void *smp_write_config_table(void *v)
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
 
 //Slot PCIE x16
-	for(i=0;i<4;i++) {
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00 << 2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
 	}
 
 //Slot  PCIE x4
-	for(i=0;i<4;i++) {
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4);
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00 << 2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4);
 	}
 
 //Onboard SM720 VGA
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (6<<2)|0, apicid_ck804, 0x13); // 19
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (6 << 2)|0, apicid_ck804, 0x13); // 19
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
 	mptable_lintsrc(mc, bus_isa);
diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c
index 20eb92e6fb..3372f3292c 100644
--- a/src/mainboard/winent/mb6047/romstage.c
+++ b/src/mainboard/winent/mb6047/romstage.c
@@ -57,7 +57,7 @@ static void sio_setup(void)
 	/* LPC Positive Decode 0 */
 	dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
 	/* Serial 0, Serial 1 */
-	dword |= (1<<0) | (1<<1);
+	dword |= (1 << 0) | (1 << 1);
 	pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
 
 }
author	Elyes HAOUAS <ehaouas@noos.fr>	2016-09-19 09:47:16 -0600
committer	Patrick Georgi <pgeorgi@google.com>	2016-09-20 21:55:12 +0200
commit	a5aad2ed68690d748c650f69a2e39f91a7b02608 (patch)
tree	7ad419bc13bcf13e546481558aa1a4c923821c07
parent	531b87ac4e8038aedf9c44c29fe2c1fc31adb346 (diff)