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authorPatrick Georgi <patrick.georgi@coresystems.de>2010-12-18 11:55:06 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2010-12-18 11:55:06 +0000
commita0360af0f1645d91b139022353f7a3a9f7f85f8a (patch)
treee7403be723e727179eed6252fdd5bb920daa9bad
parentbe61a173512ece32de01562995a91fbbf3f5b335 (diff)
A couple of Poulsbo fixes:
- Don't include cmc.bin to the build. It's required, but we don't ship it - mptable's API changes a bit. Adapt. - Fix ACPI for new iasl versions with improved code validation Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6199 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r--src/mainboard/iwave/iWRainbowG6/mptable.c2
-rw-r--r--src/northbridge/intel/sch/acpi/hostbridge.asl25
-rw-r--r--src/southbridge/intel/sch/Makefile.inc9
3 files changed, 20 insertions, 16 deletions
diff --git a/src/mainboard/iwave/iWRainbowG6/mptable.c b/src/mainboard/iwave/iWRainbowG6/mptable.c
index 09d9d9a4fd..19bd835cc6 100644
--- a/src/mainboard/iwave/iWRainbowG6/mptable.c
+++ b/src/mainboard/iwave/iWRainbowG6/mptable.c
@@ -29,7 +29,7 @@ void *smp_write_config_table(void *v)
int isa_bus;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
- mptable_init(mc, "IWRAINBOWG6", LAPIC_ADDR);
+ mptable_init(mc, LAPIC_ADDR);
smp_write_processors(mc);
mptable_write_buses(mc, NULL, &isa_bus);
diff --git a/src/northbridge/intel/sch/acpi/hostbridge.asl b/src/northbridge/intel/sch/acpi/hostbridge.asl
index a029ef524b..7e92a0e671 100644
--- a/src/northbridge/intel/sch/acpi/hostbridge.asl
+++ b/src/northbridge/intel/sch/acpi/hostbridge.asl
@@ -23,6 +23,9 @@
Name(_HID,EISAID("PNP0A08")) // PCIe
Name(_CID,EISAID("PNP0A03")) // PCI
+Name(_ADR, 0)
+Name(_BBN, 0)
+
Device (MCHC)
{
Name(_ADR, 0x00000000) // 0:0.0
@@ -204,17 +207,17 @@ Method (_CRS, 0, Serialized)
0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
0x00010000,,, FSEG)
- // PCI Memory Region (Top of memory-0xfebfffff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
- 0x00000000,,, PM01)
-
- // TPM Area (0xfed40000-0xfed44fff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
- 0x00000000,,, TPMR)
+ // PCI Memory Region (Top of memory-0xfebfffff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
+ 0xfec00000,,, PM01)
+
+ // TPM Area (0xfed40000-0xfed44fff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
+ 0x00005000,,, TPMR)
})
// Find PCI resource area in MCRS
diff --git a/src/southbridge/intel/sch/Makefile.inc b/src/southbridge/intel/sch/Makefile.inc
index 2d4d80e234..57bcf939a5 100644
--- a/src/southbridge/intel/sch/Makefile.inc
+++ b/src/southbridge/intel/sch/Makefile.inc
@@ -35,7 +35,8 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
romstage-$(CONFIG_USBDEBUG) += usb_debug.c
-cbfs-files-y += cmc.bin
-cmc.bin-name := cmc.bin
-cmc.bin-type := 0xaa
-cmc.bin-position := 0xfffd0000
+# We don't ship that, but booting without it is bound to fail
+#cbfs-files-y += cmc.bin
+#cmc.bin-name := cmc.bin
+#cmc.bin-type := 0xaa
+#cmc.bin-position := 0xfffd0000