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authorMartin Roth <martinroth@google.com>2018-05-20 17:46:51 -0600
committerMartin Roth <martinroth@google.com>2018-05-22 02:54:24 +0000
commit9641a92b112c5759ccb956287e80ba4a4983611b (patch)
treeefe2c9f7aae0756afd26600cbb584afde6c25f31
parent8f25a6680e23663f4c88f7fe61a7a62e8fe284c4 (diff)
src: Remove non-ascii characters
Change-Id: Iedb78e24a286a51830c85724af0179995ed553be Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
-rw-r--r--src/drivers/i2c/max98373/chip.h2
-rw-r--r--src/drivers/i2c/max98927/chip.h2
-rw-r--r--src/soc/intel/apollolake/include/soc/meminit.h2
-rw-r--r--src/soc/intel/cannonlake/lockdown.c4
-rw-r--r--src/soc/intel/skylake/lockdown.c4
-rw-r--r--src/soc/rockchip/rk3399/Kconfig2
-rw-r--r--src/soc/rockchip/rk3399/clock.c20
-rw-r--r--src/southbridge/via/vt8237r/acpi/default_irq_route.asl2
8 files changed, 19 insertions, 19 deletions
diff --git a/src/drivers/i2c/max98373/chip.h b/src/drivers/i2c/max98373/chip.h
index 150998b83b..ad81395238 100644
--- a/src/drivers/i2c/max98373/chip.h
+++ b/src/drivers/i2c/max98373/chip.h
@@ -19,7 +19,7 @@
struct drivers_i2c_max98373_config {
/* I2C Bus Frequency in Hertz (default 400kHz) */
uint32_t bus_speed;
- /* Set ‘1’ if I2S channel size is not 32bit. */
+ /* Set '1' if I2S channel size is not 32bit. */
bool interleave_mode;
/* Identifier for chips */
uint32_t uid;
diff --git a/src/drivers/i2c/max98927/chip.h b/src/drivers/i2c/max98927/chip.h
index 765bafdae8..6d3b9a56da 100644
--- a/src/drivers/i2c/max98927/chip.h
+++ b/src/drivers/i2c/max98927/chip.h
@@ -19,7 +19,7 @@
struct drivers_i2c_max98927_config {
/* I2C Bus Frequency in Hertz (default 400kHz) */
unsigned int bus_speed;
- /* Set ‘1’ if I2S channel size is not 32bit. */
+ /* Set '1' if I2S channel size is not 32bit. */
bool interleave_mode;
/* Identifier for chips */
unsigned int uid;
diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h
index 3b0b507ddd..27b6556d12 100644
--- a/src/soc/intel/apollolake/include/soc/meminit.h
+++ b/src/soc/intel/apollolake/include/soc/meminit.h
@@ -72,7 +72,7 @@ enum {
/*
* ODT settings :
* If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A, and HIGH for ODT_B,
- * choose ODT_AB_HIGH_HIGH. If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A,
+ * choose ODT_AB_HIGH_HIGH. If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A,
* and LOW for ODT_B, choose ODT_AB_HIGH_LOW.
*
* Note that the enum values correspond to the interpreted UPD fields
diff --git a/src/soc/intel/cannonlake/lockdown.c b/src/soc/intel/cannonlake/lockdown.c
index dba59014db..7a3b0c0130 100644
--- a/src/soc/intel/cannonlake/lockdown.c
+++ b/src/soc/intel/cannonlake/lockdown.c
@@ -60,8 +60,8 @@ static void dmi_lockdown_cfg(void)
* GCS.BBS: (Boot BIOS Strap) This field determines the destination
* of accesses to the BIOS memory range.
* Bits Description
- * “0b”: SPI
- * “1b”: LPC/eSPI
+ * "0b": SPI
+ * "1b": LPC/eSPI
*/
pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);
}
diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c
index 79f6f70987..1abe9cb884 100644
--- a/src/soc/intel/skylake/lockdown.c
+++ b/src/soc/intel/skylake/lockdown.c
@@ -57,8 +57,8 @@ static void dmi_lockdown_config(void)
* GCS.BBS: (Boot BIOS Strap) This field determines the destination
* of accesses to the BIOS memory range.
* Bits Description
- * “0b”: SPI
- * “1b”: LPC/eSPI
+ * "0b": SPI
+ * "1b": LPC/eSPI
*/
pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);
}
diff --git a/src/soc/rockchip/rk3399/Kconfig b/src/soc/rockchip/rk3399/Kconfig
index 1d2960be1f..440981bf7f 100644
--- a/src/soc/rockchip/rk3399/Kconfig
+++ b/src/soc/rockchip/rk3399/Kconfig
@@ -32,7 +32,7 @@ config RK3399_SPREAD_SPECTRUM_DDR
default n
help
Select Spread Spectrum Modulator (SSMOD) is a fully-digital circuit
- used to modulate the frequency of the Silicon Creations’ Fractional
+ used to modulate the frequency of the Silicon Creations' Fractional
PLL in order to reduce EMI.
endif
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index 980adf5000..5422deb5cf 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -344,12 +344,12 @@ static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div)
/*
* Configure the DPLL spread spectrum feature on memory clock.
* Configure sequence:
- * 1. PLL been configured as frac mode, and DACPD should be set to 1’b0.
+ * 1. PLL been configured as frac mode, and DACPD should be set to 1'b0.
* 2. Configure DOWNSPERAD, SPREAD, DIVVAL(option: configure xPLL_CON5 with
* extern wave table).
- * 3. set ssmod_disable_sscg = 1’b0, and set ssmod_bp = 1’b0.
- * 4. Assert RESET = 1’b1 to SSMOD.
- * 5. RESET = 1’b0 on SSMOD.
+ * 3. set ssmod_disable_sscg = 1'b0, and set ssmod_bp = 1'b0.
+ * 4. Assert RESET = 1'b1 to SSMOD.
+ * 5. RESET = 1'b0 on SSMOD.
* 6. Adjust SPREAD/DIVVAL/DOWNSPREAD.
*/
static void rkclk_set_dpllssc(struct pll_div *dpll_cfg)
@@ -385,13 +385,13 @@ static void rkclk_set_dpllssc(struct pll_div *dpll_cfg)
* value of SPREAD.
* SPREAD[4:0] Center Spread Down Spread
* 0 0 0
- * 1 ±0.1% -0.10%
- * 2 ±0.2% -0.20%
- * 3 ±0.3% -0.30%
- * 4 ±0.4% -0.40%
- * 5 ±0.5% -0.50%
+ * 1 +/-0.1% -0.10%
+ * 2 +/-0.2% -0.20%
+ * 3 +/-0.3% -0.30%
+ * 4 +/-0.4% -0.40%
+ * 5 +/-0.5% -0.50%
* ...
- * 31 ±3.1% -3.10%
+ * 31 +/-3.1% -3.10%
*/
write32(&cru_ptr->dpll_con[4],
RK_CLRSETBITS(PLL_SSMOD_DIVVAL_MASK << PLL_SSMOD_DIVVAL_SHIFT,
diff --git a/src/southbridge/via/vt8237r/acpi/default_irq_route.asl b/src/southbridge/via/vt8237r/acpi/default_irq_route.asl
index 2e9e76391a..351507861c 100644
--- a/src/southbridge/via/vt8237r/acpi/default_irq_route.asl
+++ b/src/southbridge/via/vt8237r/acpi/default_irq_route.asl
@@ -71,7 +71,7 @@ Method (_PRT, 0) {
Package (4) { 0x0010ffff, 2, 0x00, 21 },
Package (4) { 0x0010ffff, 3, 0x00, 21 },
- /* AC’97 / MC’97 IRQ and INTG => IRQ22 */
+ /* AC'97 / MC'97 IRQ and INTG => IRQ22 */
Package (4) { 0x0011ffff, 0, 0x00, 22 },
Package (4) { 0x0011ffff, 1, 0x00, 22 },
Package (4) { 0x0011ffff, 2, 0x00, 22 },