diff options
| author | Nico Huber <nico.huber@secunet.com> | 2017-07-06 15:06:37 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-07-11 11:35:10 +0000 |
| commit | 9413cb5f95567abc7d2846f2853504304eed1483 (patch) | |
| tree | 4bf47fb685c937d01905b6f4b140226ab9efca0c | |
| parent | c587b971ddef8270d7fbd06f5801a6fc75efe3e5 (diff) | |
soc/intel/skylake: Fix PMC address range setup for PCH-H
The PMC of PCH-H requires a different destination id.
TEST=Run on kontron/bsl6 and observed that PM registers are correctly
dumped at start of romstage.
Change-Id: I862e4df986f1cdea34f8fa45d016fb6b51f29122
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
| -rw-r--r-- | src/soc/intel/skylake/bootblock/pch.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 0b212b11b0..2502563a30 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -141,7 +141,10 @@ static void soc_config_acpibase(void) */ reg32 = ((0x3f << 18) | ACPI_BASE_ADDRESS | 1); pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32); - pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23A0); + if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)) + pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8); + else + pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a0); } static void soc_config_pwrmbase(void) @@ -172,7 +175,10 @@ static void soc_config_pwrmbase(void) pcr_write32(PID_DMI, PCR_DMI_PMBASEA, ((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) | (PCH_PWRM_BASE_ADDRESS >> 16))); - pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023A0); + if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)) + pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a8); + else + pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a0); } static void soc_config_tco(void) |