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authorLijian Zhao <lijian.zhao@intel.com>2018-03-12 18:05:53 -0700
committerMartin Roth <martinroth@google.com>2018-04-05 16:00:27 +0000
commit91c8e23e013204d415582b6ff2444ba5e3021306 (patch)
tree049e4d68daceda0fc98a50d422f8a0fa40702efe
parent32c3069fd7d076a41ceb5a0453bd9ec1ec9f8559 (diff)
soc/intel/cannonlake: Add VT-d and VMX programming
Add FSP option to enable/disable VT-d (Intel Virtualization Technology for Directed I/O) and VMX (Virtual Machine Extensions), VMX will be disabled once VT-d got disabled. Bug=b:73655383 TEST=Build and flash image on meowth board with debug build FSP, in serial log search for "VMXEnable" and "VtdDiable". Change-Id: I589590450aa4b9302ee2f9bb7b879a332f50b73e Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/25118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/soc/intel/cannonlake/chip.c4
-rw-r--r--src/soc/intel/cannonlake/chip.h4
-rw-r--r--src/soc/intel/cannonlake/romstage/romstage.c5
3 files changed, 13 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 590bb4559d..5fc3a55c26 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -181,6 +181,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
{
int i;
FSP_S_CONFIG *params = &supd->FspsConfig;
+ FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig;
struct device *dev = SA_DEV_ROOT;
config_t *config = dev->chip_info;
@@ -300,6 +301,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
* 3 = GT unsliced, 4 = GT sliced */
for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)
fill_vr_domain_config(params, i, &config->domain_vr_config[i]);
+
+ /* Vt-D config */
+ tconfig->VtdDisable = config->VtdDisable;
}
/* Mainboard GPIO Configuration */
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 2362c4255e..8fdb9646b3 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -281,6 +281,10 @@ struct soc_intel_cannonlake_config {
/* Enable Pch iSCLK */
uint8_t pch_isclk;
+
+ /* Intel VT configuration */
+ uint8_t VtdDisable;
+ uint8_t VmxEnable;
};
typedef struct soc_intel_cannonlake_config config_t;
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 759c2c9b43..dc9652689a 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -169,6 +169,11 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
/* Disable Cpu Ratio Override temporary. */
m_cfg->CpuRatio = 0;
m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE;
+ /* Disable Vmx if Vt-d is already disabled */
+ if (config->VtdDisable)
+ m_cfg->VmxEnable = 0;
+ else
+ m_cfg->VmxEnable = config->VmxEnable;
}
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)