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authorFelix Held <felix-coreboot@felixheld.de>2020-01-26 04:55:27 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-01-27 07:47:56 +0000
commit87ddea26cf1e8fce25e33c4f2db2533e0f612ac7 (patch)
treec238b95bfb62d3b5630caf59a6b1652ed343b65d
parent3f3b4d5d74c4c9d4f01c7035c8626032cb9a6b56 (diff)
nb/intel/sandybridge: replace NORTHBRIDGE with HOST_BRIDGE define
The two defines are identical, so deduplicate this. Timeless build for lenovo/x230 results in identical binary. Change-Id: I32e0eee88d72eb6f8dc71b0324d62f46079120a9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
-rw-r--r--src/northbridge/intel/sandybridge/raminit_common.c3
-rw-r--r--src/northbridge/intel/sandybridge/raminit_common.h5
2 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index c69c827136..7136cd42d2 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -497,7 +497,6 @@ void dram_zones(ramctr_timing *ctrl, int training)
}
}
-#define HOST_BRIDGE PCI_DEV(0, 0, 0)
#define DEFAULT_TCK TCK_800MHZ
unsigned int get_mem_min_tck(void)
@@ -595,7 +594,7 @@ void dram_memorymap(ramctr_timing *ctrl, int me_uma_size)
mmiosize = get_mmio_size();
- ggc = pci_read_config16(NORTHBRIDGE, GGC);
+ ggc = pci_read_config16(HOST_BRIDGE, GGC);
if (!(ggc & 2)) {
gfxstolen = ((ggc >> 3) & 0x1f) * 32;
gttsize = ((ggc >> 8) & 0x3);
diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h
index 194e6db673..6d3af877b5 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.h
+++ b/src/northbridge/intel/sandybridge/raminit_common.h
@@ -136,8 +136,9 @@ typedef struct ramctr_timing_st {
dimm_info info;
} ramctr_timing;
-#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
-#define NORTHBRIDGE PCI_DEV(0, 0x0, 0)
+#define HOST_BRIDGE PCI_DEV(0, 0, 0)
+#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
+
#define FOR_ALL_LANES for (lane = 0; lane < NUM_LANES; lane++)
#define FOR_ALL_CHANNELS for (channel = 0; channel < NUM_CHANNELS; channel++)
#define FOR_ALL_POPULATED_RANKS for (slotrank = 0; slotrank < NUM_SLOTRANKS; slotrank++) if (ctrl->rankmap[channel] & (1 << slotrank))