start of port of adl855pc

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 137 insertions, 1 deletions

diff --git a/src/mainboard/digitallogic/adl855pc/Config.lb b/src/mainboard/digitallogic/adl855pc/Config.lb
index 62002fdc04..1de157c1e5 100644
--- a/src/mainboard/digitallogic/adl855pc/Config.lb
+++ b/src/mainboard/digitallogic/adl855pc/Config.lb
@@ -213,7 +213,7 @@ config chip.h
 northbridge intel/855pm "855pm"
 #	pci 0:0.0
 #	pci 0:1.0
-	southbridge via/vt8231 "vt8231"
+	southbridge intel/i82801dbm "i82801dbm"
 #		pci 0:11.0
 #		pci 0:11.1
 #		pci 0:11.2
diff --git a/src/mainboard/via/epia/Config.lb b/src/mainboard/via/epia/Config.lb
index 0450b2b1b9..30bd43b86c 100644
--- a/src/mainboard/via/epia/Config.lb
+++ b/src/mainboard/via/epia/Config.lb
@@ -227,6 +227,36 @@ northbridge via/vt8601 "vt8601"
 		register "enable_com_ports" = "1"
 		register "enable_keyboard" = "0"
 		register "enable_nvram" = "1"
+                superio winbond/w83627hf link 1
+                        pnp 2e.0 on #  Floppy
+                                 io 0x60 = 0x3f0
+                                irq 0x70 = 6
+                                drq 0x74 = 2
+                        pnp 2e.1 off #  Parallel Port
+                                 io 0x60 = 0x378
+                                irq 0x70 = 7
+                        pnp 2e.2 on #  Com1
+                                 io 0x60 = 0x3f8
+                                irq 0x70 = 4
+                        pnp 2e.3 off #  Com2
+                                io 0x60 = 0x2f8
+                                irq 0x70 = 3
+                        pnp 2e.5 on #  Keyboard
+                                 io 0x60 = 0x60
+                                 io 0x62 = 0x64
+                               irq 0x70 = 1
+				irq 0x72 = 12
+                        pnp 2e.6 off #  CIR
+                        pnp 2e.7 off #  GAME_MIDI_GIPO1
+                        pnp 2e.8 off #  GPIO2
+                        pnp 2e.9 off #  GPIO3
+                        pnp 2e.a off #  ACPI
+                        pnp 2e.b on  #  HW Monitor
+ 				 io 0x60 = 0x290
+			register "com1" = "{1}"
+		#	register "com1" = "{1, 0, 0x3f8, 4}"
+		#	register "lpt" = "{1}"
+                end
 	end
 end
 
diff --git a/targets/digitallogic/adl855pc/Config.lb b/targets/digitallogic/adl855pc/Config.lb
new file mode 100644
index 0000000000..6ff68b77db
--- /dev/null
+++ b/targets/digitallogic/adl855pc/Config.lb
@@ -0,0 +1,106 @@
+# Sample config file for adl855pc
+# This will make a target directory of ./adl855pc
+
+loadoptions
+
+target adl855pc
+
+uses ARCH
+uses CONFIG_COMPRESS
+uses CONFIG_IOAPIC
+uses CONFIG_ROM_STREAM
+uses CONFIG_ROM_STREAM_START
+uses CONFIG_UDELAY_TSC
+uses CPU_FIXUP
+uses FALLBACK_SIZE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses HAVE_HARD_RESET
+uses i586
+uses i686
+uses INTEL_PPRO_MTRR
+uses HEAP_SIZE
+uses IRQ_SLOT_COUNT
+uses MAINBOARD_PART_NUMBER
+uses MAINBOARD_VENDOR
+uses CONFIG_SMP
+uses CONFIG_MAX_CPUS
+uses MEMORY_HOLE
+uses PAYLOAD_SIZE
+uses _RAMBASE
+uses _ROMBASE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_OFFSET
+uses ROM_SECTION_SIZE
+uses ROM_SIZE
+uses STACK_SIZE
+uses USE_FALLBACK_IMAGE
+uses USE_OPTION_TABLE
+uses HAVE_OPTION_TABLE
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses  DEFAULT_CONSOLE_LOGLEVEL
+uses  CONFIG_CONSOLE_SERIAL8250
+uses MAINBOARD
+uses CONFIG_CHIP_CONFIGURE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses LINUXBIOS_EXTRA_VERSION
+uses TTYS0_BAUD
+
+option TTYS0_BAUD=115200
+
+option CONFIG_CHIP_CONFIGURE=1
+
+option  MAXIMUM_CONSOLE_LOGLEVEL=7
+option  DEFAULT_CONSOLE_LOGLEVEL=7
+option  CONFIG_CONSOLE_SERIAL8250=1
+
+option CPU_FIXUP=1
+option CONFIG_UDELAY_TSC=0
+option i686=1
+option i586=1
+option INTEL_PPRO_MTRR=1
+option ROM_SIZE=256*1024
+
+option HAVE_OPTION_TABLE=1
+option CONFIG_ROM_STREAM=1
+option HAVE_FALLBACK_BOOT=1
+
+###
+### Compute the location and size of where this firmware image
+### (linuxBIOS plus bootloader) will live in the boot rom chip.
+###
+option FALLBACK_SIZE=131072
+
+## LinuxBIOS C code runs at this location in RAM
+option _RAMBASE=0x00004000
+
+#
+###
+### Compute the start location and size size of
+### The linuxBIOS bootloader.
+###
+
+#
+romimage "normal"
+	option USE_FALLBACK_IMAGE=0
+	option ROM_IMAGE_SIZE=0x10000
+	option LINUXBIOS_EXTRA_VERSION=".0Normal"
+	mainboard digitallogic/adl855pc
+#	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
+#	payload ../../../../tg3--ide_disk.zelf	
+	payload ../../../../../lnxieepro100.ebi
+end
+
+romimage "fallback" 
+	option USE_FALLBACK_IMAGE=1
+	option ROM_IMAGE_SIZE=0x10000
+	option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+	mainboard digitallogic/adl855pc
+#	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
+#	payload ../../../../tg3--ide_disk.zelf	
+	payload ../../../../../lnxieepro100.ebi
+end
+
+buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"