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authorNaresh G Solanki <naresh.solanki@intel.com>2016-11-16 21:32:04 +0530
committerAaron Durbin <adurbin@chromium.org>2016-11-30 16:59:10 +0100
commit721d1b30907d379b1d1cb095f4157229fcedd433 (patch)
treed0e2e0089d42a247d9bf8ae320621c9a21edbce8
parent6467014046811d86a86e4f143476787a4c35a8cc (diff)
soc/intel/skylake: Fix top_of_ram calculation
FSP 2.0 implementation conditionally sets PMRR base based on EnableC6Dram UPD. Therefore, handle the case of the PMRR base not being set since FSP 2.0 changed behavior from FSP 1.1 implementation. If prmrr base is non-zero value, then top_of_ram is prmrr base. If Probeless trace is enabled, then deduct trace memory size from calculated top_of_ram. Change-Id: I2633bf78705e36b241668a313d215d0455fba607 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17554 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/soc/intel/skylake/memmap.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index 96debfd53f..17dbc320c6 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -150,7 +150,8 @@ u32 top_of_32bit_ram(void)
* PRMMR_BASE MSR. The system hangs if PRMRR_BASE MSR is read before
* PRMRR_MASK MSR lock bit is set.
*/
- if (smm_region_start() == 0)
+ top_of_ram = smm_region_start();
+ if (top_of_ram == 0)
return 0;
dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_ROOT, 0));
@@ -163,7 +164,8 @@ u32 top_of_32bit_ram(void)
* Refer to Fsp Integration Guide for the memory mapping layout.
*/
prmrr_base = rdmsr(UNCORE_PRMRR_PHYS_BASE_MSR);
- top_of_ram = prmrr_base.lo;
+ if (prmrr_base.lo)
+ top_of_ram = prmrr_base.lo;
if (config->ProbelessTrace)
top_of_ram -= TRACE_MEMORY_SIZE;