summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorDuncan Laurie <dlaurie@chromium.org>2014-02-11 10:34:06 -0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2014-02-12 23:31:19 +0100
commit6c03160d48f9b2d1dfaf5a193893b011e71ac30e (patch)
treed7fe4cb982837ebd961b5116d2b9c5a7d3b6ee51
parent2161c1d792fedecfad32587b6fde657c19d647d0 (diff)
lynxpoint: Do not put SerialIO devices into D3Hot in ACPI mode
Remove the bit of code that was putting the SerialIO devices into D3Hot state when they are switched from PCI to ACPI mode. Instead, add the appropriate ACPI Methods to allow the kernel to control the power state of the device. The problem seems to be that if the device is put in D3Hot state before it is switched from PCI to ACPI mode then it does not properly export its PCI configuration space and cannot be woken back up. Adding the ACPI Methods for _PS0/_PS3 allows the kernel to transition the device into D0 state only when it is necessary to communicate with the device, then put it back into D3Hot state. Change-Id: I2384ba10bf47750d1c1a35216169ddeee26881df Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5193 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/southbridge/intel/lynxpoint/acpi/serialio.asl44
-rw-r--r--src/southbridge/intel/lynxpoint/serialio.c10
2 files changed, 44 insertions, 10 deletions
diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl
index 4c0d36bcc6..59228d6cf5 100644
--- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl
@@ -211,6 +211,28 @@ Device (I2C0)
Return (0xF)
}
}
+
+ // Access to PCI Config in ACPI mode
+ OperationRegion (KEYS, SystemMemory, \S1B1, 0x100)
+ Field (KEYS, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x84),
+ PSAT, 32,
+ }
+
+ // Put controller in D0 state
+ Method (_PS0, 0, Serialized)
+ {
+ And (^PSAT, 0xfffffffc, ^PSAT)
+ Store (^PSAT, Local0)
+ }
+
+ // Put controller in D3Hot state
+ Method (_PS3, 0, Serialized)
+ {
+ Or (^PSAT, 0x00000003, ^PSAT)
+ Store (^PSAT, Local0)
+ }
}
Device (I2C1)
@@ -262,6 +284,28 @@ Device (I2C1)
Return (0xF)
}
}
+
+ // Access to PCI Config in ACPI mode
+ OperationRegion (KEYS, SystemMemory, \S2B1, 0x100)
+ Field (KEYS, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x84),
+ PSAT, 32,
+ }
+
+ // Put controller in D0 state
+ Method (_PS0, 0, Serialized)
+ {
+ And (^PSAT, 0xfffffffc, ^PSAT)
+ Store (^PSAT, Local0)
+ }
+
+ // Put controller in D3Hot state
+ Method (_PS3, 0, Serialized)
+ {
+ Or (^PSAT, 0x00000003, ^PSAT)
+ Store (^PSAT, Local0)
+ }
}
Device (SPI0)
diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c
index 8257cc2f6f..75edf5c9db 100644
--- a/src/southbridge/intel/lynxpoint/serialio.c
+++ b/src/southbridge/intel/lynxpoint/serialio.c
@@ -29,14 +29,6 @@
#include "pch.h"
#include "nvs.h"
-/* Set D3Hot Power State in ACPI mode */
-static void serialio_enable_d3hot(struct device *dev)
-{
- u32 reg32 = pci_read_config32(dev, PCH_PCS);
- reg32 |= PCH_PCS_PS_D3HOT;
- pci_write_config32(dev, PCH_PCS, reg32);
-}
-
/* Enable clock in PCI mode */
static void serialio_enable_clock(struct resource *bar0)
{
@@ -178,8 +170,6 @@ static void serialio_init(struct device *dev)
if (!config->sio_acpi_mode)
serialio_enable_clock(bar0);
- else if (dev->path.pci.devfn != PCI_DEVFN(21, 0))
- serialio_enable_d3hot(dev); /* all but SDMA */
switch (dev->path.pci.devfn) {
case PCI_DEVFN(21, 0): /* SDMA */