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authorRizwan Qureshi <rizwan.qureshi@intel.com>2017-09-05 14:18:25 +0530
committerAaron Durbin <adurbin@chromium.org>2017-09-06 16:39:58 +0000
commit6ab4ed40d355a55f0ff8e8aade55be796a256c0d (patch)
tree94099a66ca3f6172e5ecfbab60acc77b70de194c
parent33f1273f9f1e41c1c7f42732dd9430e40476abc3 (diff)
soc/intel/skylake: Add config for enabling PCIe AER
Add a config for enabling/disabling Advanced Error Reporting feature for PCIe root ports. BUG=b:64798078 TEST="lspci" shows that AER is enabled in the capabilities list. Change-Id: Ieb74c3566ded2276e549c98f78813c4f5d4d310a Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
-rw-r--r--src/soc/intel/skylake/chip.h1
-rw-r--r--src/soc/intel/skylake/chip_fsp20.c3
2 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index beb5a7aa0b..45f3f9982a 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -173,6 +173,7 @@ struct soc_intel_skylake_config {
u8 PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
u8 PcieRpClkReqSupport[CONFIG_MAX_ROOT_PORTS];
u8 PcieRpClkReqNumber[CONFIG_MAX_ROOT_PORTS];
+ u8 PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];
/* USB related */
struct usb2_port_config usb2_ports[16];
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index aa612ede0a..adf87723dc 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -166,6 +166,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
sizeof(params->PcieRpClkReqSupport));
memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber,
sizeof(params->PcieRpClkReqNumber));
+ memcpy(params->PcieRpAdvancedErrorReporting,
+ config->PcieRpAdvancedErrorReporting,
+ sizeof(params->PcieRpAdvancedErrorReporting));
/* disable Legacy PME */
memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));