diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-07 17:45:12 -0800 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-13 17:23:37 +0100 |
| commit | 6a566d7fbee8e81fa22916a29339e5991872edfb (patch) | |
| tree | 21840b8f2965439422e809ab56f9ef19cdccf4bd | |
| parent | d0f26fcea2fdab02d9b9fc1fceb9e782694a55bc (diff) | |
src/include: Wrap lines at 80 columns
Fix the following warning detected by checkpatch.pl:
WARNING: line over 80 characters
Changed a few comments to reduce line length. File
src/include/cpu/amd/vr.h was skipped.
TEST=Build and run on Galileo Gen2
Change-Id: Ie3c07111acc1f89923fb31135684a6d28a505b61
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18687
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
37 files changed, 472 insertions, 253 deletions
diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 1350671af2..1dac504242 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -50,7 +50,9 @@ size_t cbfs_boot_load_struct(const char *name, void *buf, size_t buf_size); size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset, size_t in_size, void *buffer, size_t buffer_size, uint32_t compression); -/* Return the size and fill base of the memory pstage will occupy after loaded. */ +/* Return the size and fill base of the memory pstage will occupy after + * loaded. + */ size_t cbfs_prog_stage_section(struct prog *pstage, uintptr_t *base); /* Load stage into memory filling in prog. Return 0 on success. < 0 on error. */ diff --git a/src/include/console/console.h b/src/include/console/console.h index 7edce52ff8..3100ae2d55 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -48,7 +48,8 @@ void __attribute__ ((noreturn)) die(const char *msg); #if __CONSOLE_ENABLE__ asmlinkage void console_init(void); int console_log_level(int msg_level); -int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); +int do_printk(int msg_level, const char *fmt, ...) + __attribute__((format(printf, 2, 3))); void do_putchar(unsigned char byte); #define printk(LEVEL, fmt, args...) \ diff --git a/src/include/console/early_print.h b/src/include/console/early_print.h index cde501a4ec..2e6a2461b7 100644 --- a/src/include/console/early_print.h +++ b/src/include/console/early_print.h @@ -25,7 +25,8 @@ /* While in romstage, console loglevel is built-time constant. * With ROMCC we inline this test with help from preprocessor. */ -#define console_log_level(msg_level) (msg_level <= CONFIG_DEFAULT_CONSOLE_LOGLEVEL) +#define console_log_level(msg_level) \ + (msg_level <= CONFIG_DEFAULT_CONSOLE_LOGLEVEL) #define CALL_CONSOLE_TX(loglevel, tx_func, x) \ do { \ @@ -35,11 +36,16 @@ } \ } while (0) -#define __console_tx_char(level, x) CALL_CONSOLE_TX(level, console_tx_byte, x) -#define __console_tx_hex8(level, x) CALL_CONSOLE_TX(level, console_tx_hex8, x) -#define __console_tx_hex16(level, x) CALL_CONSOLE_TX(level, console_tx_hex16, x) -#define __console_tx_hex32(level, x) CALL_CONSOLE_TX(level, console_tx_hex32, x) -#define __console_tx_string(level, x) CALL_CONSOLE_TX(level, console_tx_string, x) +#define __console_tx_char(level, x) \ + CALL_CONSOLE_TX(level, console_tx_byte, x) +#define __console_tx_hex8(level, x) \ + CALL_CONSOLE_TX(level, console_tx_hex8, x) +#define __console_tx_hex16(level, x) \ + CALL_CONSOLE_TX(level, console_tx_hex16, x) +#define __console_tx_hex32(level, x) \ + CALL_CONSOLE_TX(level, console_tx_hex32, x) +#define __console_tx_string(level, x) \ + CALL_CONSOLE_TX(level, console_tx_string, x) #define print_emerg(STR) __console_tx_string(BIOS_EMERG, STR) #define print_alert(STR) __console_tx_string(BIOS_ALERT, STR) diff --git a/src/include/console/ne2k.h b/src/include/console/ne2k.h index d7974b5a33..ea2a139ad2 100644 --- a/src/include/console/ne2k.h +++ b/src/include/console/ne2k.h @@ -28,9 +28,18 @@ void ne2k_transmit(unsigned int eth_nic_base); #endif #if CONFIG_CONSOLE_NE2K && (ENV_ROMSTAGE || ENV_RAMSTAGE) -static inline void __ne2k_init(void) { ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT); } -static inline void __ne2k_tx_byte(u8 data) { ne2k_append_data_byte(data, CONFIG_CONSOLE_NE2K_IO_PORT); } -static inline void __ne2k_tx_flush(void) { ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); } +static inline void __ne2k_init(void) +{ + ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT); +} +static inline void __ne2k_tx_byte(u8 data) +{ + ne2k_append_data_byte(data, CONFIG_CONSOLE_NE2K_IO_PORT); +} +static inline void __ne2k_tx_flush(void) +{ + ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); +} #else static inline void __ne2k_init(void) {} static inline void __ne2k_tx_byte(u8 data) {} diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index e1a640cab7..f08796cf72 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -347,12 +347,13 @@ /* * The following POST codes are taken from src/include/cpu/amd/geode_post_code.h * They overlap with previous codes, and most are not even used - * Some mainboards still require them, but they are deprecated. We want to consolidate - * our own POST code structure with the codes above. + * Some mainboards still require them, but they are deprecated. We want to + * consolidate our own POST code structure with the codes above. * * standard AMD post definitions for the AMD Geode */ -#define POST_Output_Port (0x080) /* port to write post codes to*/ +/* port to write post codes to */ +#define POST_Output_Port (0x080) #define POST_preSioInit (0x000) #define POST_clockInit (0x001) diff --git a/src/include/console/qemu_debugcon.h b/src/include/console/qemu_debugcon.h index 257ae581e5..544442a662 100644 --- a/src/include/console/qemu_debugcon.h +++ b/src/include/console/qemu_debugcon.h @@ -9,7 +9,10 @@ void qemu_debugcon_tx_byte(unsigned char data); #if CONFIG_CONSOLE_QEMU_DEBUGCON && (ENV_ROMSTAGE || ENV_RAMSTAGE) static inline void __qemu_debugcon_init(void) { qemu_debugcon_init(); } -static inline void __qemu_debugcon_tx_byte(u8 data) { qemu_debugcon_tx_byte(data); } +static inline void __qemu_debugcon_tx_byte(u8 data) +{ + qemu_debugcon_tx_byte(data); +} #else static inline void __qemu_debugcon_init(void) {} static inline void __qemu_debugcon_tx_byte(u8 data) {} diff --git a/src/include/console/spi.h b/src/include/console/spi.h index 32741fbdd8..4d281acd77 100644 --- a/src/include/console/spi.h +++ b/src/include/console/spi.h @@ -27,7 +27,10 @@ void spiconsole_tx_byte(unsigned char c); #if __CONSOLE_SPI_ENABLE__ static inline void __spiconsole_init(void) { spiconsole_init(); } -static inline void __spiconsole_tx_byte(u8 data) { spiconsole_tx_byte(data); } +static inline void __spiconsole_tx_byte(u8 data) +{ + spiconsole_tx_byte(data); +} #else static inline void __spiconsole_init(void) {} static inline void __spiconsole_tx_byte(u8 data) {} diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 45faf0ad6f..07ac763932 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -60,9 +60,18 @@ void oxford_remap(unsigned int new_base); ENV_POSTCAR || (ENV_SMM && CONFIG_DEBUG_SMI))) #if __CONSOLE_SERIAL_ENABLE__ -static inline void __uart_init(void) { uart_init(CONFIG_UART_FOR_CONSOLE); } -static inline void __uart_tx_byte(u8 data) { uart_tx_byte(CONFIG_UART_FOR_CONSOLE, data); } -static inline void __uart_tx_flush(void) { uart_tx_flush(CONFIG_UART_FOR_CONSOLE); } +static inline void __uart_init(void) +{ + uart_init(CONFIG_UART_FOR_CONSOLE); +} +static inline void __uart_tx_byte(u8 data) +{ + uart_tx_byte(CONFIG_UART_FOR_CONSOLE, data); +} +static inline void __uart_tx_flush(void) +{ + uart_tx_flush(CONFIG_UART_FOR_CONSOLE); +} #else static inline void __uart_init(void) {} static inline void __uart_tx_byte(u8 data) {} @@ -72,9 +81,15 @@ static inline void __uart_tx_flush(void) {} #if CONFIG_GDB_STUB && (ENV_ROMSTAGE || ENV_RAMSTAGE) #define CONFIG_UART_FOR_GDB CONFIG_UART_FOR_CONSOLE static inline void __gdb_hw_init(void) { uart_init(CONFIG_UART_FOR_GDB); } -static inline void __gdb_tx_byte(u8 data) { uart_tx_byte(CONFIG_UART_FOR_GDB, data); } +static inline void __gdb_tx_byte(u8 data) +{ + uart_tx_byte(CONFIG_UART_FOR_GDB, data); +} static inline void __gdb_tx_flush(void) { uart_tx_flush(CONFIG_UART_FOR_GDB); } -static inline u8 __gdb_rx_byte(void) { return uart_rx_byte(CONFIG_UART_FOR_GDB); } +static inline u8 __gdb_rx_byte(void) +{ + return uart_rx_byte(CONFIG_UART_FOR_GDB); +} #endif #endif /* __ROMCC__ */ diff --git a/src/include/console/usb.h b/src/include/console/usb.h index d52ea87536..1b153ef8e6 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -35,7 +35,10 @@ int usb_can_rx_byte(int idx); #if __CONSOLE_USB_ENABLE__ static inline void __usbdebug_init(void) { usbdebug_init(); } -static inline void __usb_tx_byte(u8 data) { usb_tx_byte(USB_PIPE_FOR_CONSOLE, data); } +static inline void __usb_tx_byte(u8 data) +{ + usb_tx_byte(USB_PIPE_FOR_CONSOLE, data); +} static inline void __usb_tx_flush(void) { usb_tx_flush(USB_PIPE_FOR_CONSOLE); } #else static inline void __usbdebug_init(void) {} @@ -47,9 +50,15 @@ static inline void __usb_tx_flush(void) {} #if 0 && CONFIG_GDB_STUB && \ ((ENV_ROMSTAGE && CONFIG_USBDEBUG_IN_ROMSTAGE) || ENV_RAMSTAGE) static inline void __gdb_hw_init(void) { usbdebug_init(); } -static inline void __gdb_tx_byte(u8 data) { usb_tx_byte(USB_PIPE_FOR_GDB, data); } +static inline void __gdb_tx_byte(u8 data) +{ + usb_tx_byte(USB_PIPE_FOR_GDB, data); +} static inline void __gdb_tx_flush(void) { usb_tx_flush(USB_PIPE_FOR_GDB); } -static inline u8 __gdb_rx_byte(void) { return usb_rx_byte(USB_PIPE_FOR_GDB); } +static inline u8 __gdb_rx_byte(void) +{ + return usb_rx_byte(USB_PIPE_FOR_GDB); +} #endif #endif /* _CONSOLE_USB_H_ */ diff --git a/src/include/cpu/amd/amdfam10_sysconf.h b/src/include/cpu/amd/amdfam10_sysconf.h index bff65ec917..a60dae3c99 100644 --- a/src/include/cpu/amd/amdfam10_sysconf.h +++ b/src/include/cpu/amd/amdfam10_sysconf.h @@ -40,7 +40,8 @@ struct amdfam10_sysconf_t { unsigned int nodes; unsigned int ht_c_num; // we only can have 32 ht chain at most - unsigned int ht_c_conf_bus[HC_NUMS]; // 4-->32: 4:segn, 8:bus_max, 8:bus_min, 4:linkn, 6: nodeid, 2: enable + // 4-->32: 4:segn, 8:bus_max, 8:bus_min, 4:linkn, 6: nodeid, 2: enable + unsigned int ht_c_conf_bus[HC_NUMS]; unsigned int io_addr_num; unsigned int conf_io_addr[HC_NUMS]; unsigned int conf_io_addrx[HC_NUMS]; @@ -50,7 +51,8 @@ struct amdfam10_sysconf_t { unsigned int segbit; unsigned int hcdn_reg[HC_NUMS]; // it will be used by get_pci1234 - msr_t msr_pstate[NODE_NUMS * 5]; // quad cores all cores in one node should be the same, and p0,..p5 + // quad cores all cores in one node should be the same, and p0,..p5 + msr_t msr_pstate[NODE_NUMS * 5]; unsigned int needs_update_pstate_msrs; unsigned int bsp_apicid; diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h index 6a40d62e4b..330da8526e 100644 --- a/src/include/cpu/amd/gx2def.h +++ b/src/include/cpu/amd/gx2def.h @@ -78,10 +78,14 @@ #define GL1_PCI 4 #define GL1_FG 5 -#define MSR_GLIU0 ((GL0_GLIU0 << 29) + (1 << 28)) /* 1000xxxx - To get on GeodeLink one bit has to be set */ +/* 1000xxxx - To get on GeodeLink one bit has to be set */ +#define MSR_GLIU0 ((GL0_GLIU0 << 29) + (1 << 28)) #define MSR_MC (GL0_MC << 29) /* 2000xxxx */ #define MSR_GLIU1 (GL0_GLIU1 << 29) /* 4000xxxx */ -#define MSR_CPU (GL0_CPU << 29) /* 6000xxxx - this is not used for BIOS since code executing on CPU doesn't need to be routed */ +/* 6000xxxx - this is not used for BIOS since code executing on CPU doesn't + * need to be routed + */ +#define MSR_CPU (GL0_CPU << 29) #define MSR_VG (GL0_VG << 29) /* 8000xxxx */ #define MSR_GP (GL0_GP << 29) /* A000xxxx */ #define MSR_DF (GL0_DF << 29) /* C000xxxx */ @@ -293,7 +297,7 @@ #define RSTPLL_UPPER_VDIV_SHIFT 6 #define RSTPLL_UPPER_FBDIV_SHIFT 0 #define RSTPLL_LOWER_SWFLAGS_SHIFT 26 -#define RSTPLL_LOWER_SWFLAGS_MASK (0x3F<<RSTPLL_LOWER_SWFLAGS_SHIFT) +#define RSTPLL_LOWER_SWFLAGS_MASK (0x3F<<RSTPLL_LOWER_SWFLAGS_SHIFT) #define RSTPPL_LOWER_HOLD_COUNT_SHIFT 16 #define RSTPPL_LOWER_BYPASS_SHIFT 15 #define RSTPPL_LOWER_TST_SHIFT 11 @@ -392,15 +396,23 @@ #define MAX_COL_ADDR 17 /* more fun stuff */ -#define BM 1 /* Base Mask - map power of 2 size aligned region */ +/* Base Mask - map power of 2 size aligned region */ +#define BM 1 #define BMO 2 /* BM with an offset */ #define R 3 /* Range - 4k range minimum */ #define RO 4 /* R with offset */ -#define SC 5 /* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R */ +/* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R */ +#define SC 5 #define BMIO 6 /* Base Mask IO */ #define SCIO 7 /* Swiss 0xCeese IO */ -#define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independent of CPU */ -#define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independent of CPU */ +/* Special marker for Shadow SC descriptors so setShadow proc is independent + * of CPU + */ +#define SC_SHADOW 8 +/* Special marker for SYSMEM R descriptors so GLIUInit proc is independent + * of CPU + */ +#define R_SYSMEM 9 #define BMO_SMM 10 /* Special marker for SMM */ #define BM_SMM 11 /* Special marker for SMM */ #define BMO_DMM 12 /* Special marker for DMM */ @@ -415,33 +427,33 @@ /* Set up desc addresses from 20 - E8 */ /* This is chip specific! */ //remove after MSRINIT is gone -#define MSR_GLIU0_BASE1 (MSR_GLIU0 + 0x20) /* BM */ -#define MSR_GLIU0_BASE2 (MSR_GLIU0 + 0x21) /* BM */ -#define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC */ -#define MSR_GLIU0_SYSMEM (MSR_GLIU0 + 0x28) /* RO should only be R */ - -#define MSR_GLIU1_BASE1 (MSR_GLIU1 + 0x20) /* BM */ -#define MSR_GLIU1_BASE2 (MSR_GLIU1 + 0x21) /* BM */ -#define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2D) /* SCO should only be SC */ -#define MSR_GLIU1_SYSMEM (MSR_GLIU1 + 0x29) /* RO should only be R */ - -#define GLIU0_P2D_BM_0 (MSR_GLIU0 + 0x20) /* BASE1 */ -#define GLIU0_P2D_BM_1 (MSR_GLIU0 + 0x21) /* BASE2 */ +#define MSR_GLIU0_BASE1 (MSR_GLIU0 + 0x20) /* BM */ +#define MSR_GLIU0_BASE2 (MSR_GLIU0 + 0x21) /* BM */ +#define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC */ +#define MSR_GLIU0_SYSMEM (MSR_GLIU0 + 0x28) /* RO should only be R */ + +#define MSR_GLIU1_BASE1 (MSR_GLIU1 + 0x20) /* BM */ +#define MSR_GLIU1_BASE2 (MSR_GLIU1 + 0x21) /* BM */ +#define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2D) /* SCO should only be SC */ +#define MSR_GLIU1_SYSMEM (MSR_GLIU1 + 0x29) /* RO should only be R */ + +#define GLIU0_P2D_BM_0 (MSR_GLIU0 + 0x20) /* BASE1 */ +#define GLIU0_P2D_BM_1 (MSR_GLIU0 + 0x21) /* BASE2 */ #define GLIU0_P2D_BM_2 (MSR_GLIU0 + 0x22) #define GLIU0_P2D_BM_3 (MSR_GLIU0 + 0x23) #define GLIU0_P2D_BM_4 (MSR_GLIU0 + 0x24) #define GLIU0_P2D_BM_5 (MSR_GLIU0 + 0x25) -#define GLIU0_P2D_BMO_0 (MSR_GLIU0 + 0x26) /* SMM */ -#define GLIU0_P2D_BMO_1 (MSR_GLIU0 + 0x27) /* DMM */ +#define GLIU0_P2D_BMO_0 (MSR_GLIU0 + 0x26) /* SMM */ +#define GLIU0_P2D_BMO_1 (MSR_GLIU0 + 0x27) /* DMM */ -#define GLIU0_P2D_R_0 (MSR_GLIU0 + 0x28) /* SYSMEM */ +#define GLIU0_P2D_R_0 (MSR_GLIU0 + 0x28) /* SYSMEM */ #define GLIU0_P2D_RO_0 (MSR_GLIU0 + 0x29) #define GLIU0_P2D_RO_1 (MSR_GLIU0 + 0x2A) #define GLIU0_P2D_RO_2 (MSR_GLIU0 + 0x2B) -#define GLIU0_P2D_SC_0 (MSR_GLIU0 + 0x2C) /* SHADOW */ +#define GLIU0_P2D_SC_0 (MSR_GLIU0 + 0x2C) /* SHADOW */ #define GLIU0_IOD_BM_0 (MSR_GLIU0 + 0xE0) #define GLIU0_IOD_BM_1 (MSR_GLIU0 + 0xE1) @@ -454,28 +466,28 @@ #define GLIU0_IOD_SC_4 (MSR_GLIU0 + 0xE7) #define GLIU0_IOD_SC_5 (MSR_GLIU0 + 0xE8) -#define GLIU1_P2D_BM_0 (MSR_GLIU1 + 0x20) /* BASE1 */ -#define GLIU1_P2D_BM_1 (MSR_GLIU1 + 0x21) /* BASE2 */ +#define GLIU1_P2D_BM_0 (MSR_GLIU1 + 0x20) /* BASE1 */ +#define GLIU1_P2D_BM_1 (MSR_GLIU1 + 0x21) /* BASE2 */ #define GLIU1_P2D_BM_2 (MSR_GLIU1 + 0x22) -#define GLIU1_P2D_BM_3 (MSR_GLIU1 + 0x23) /* SMM */ -#define GLIU1_P2D_BM_4 (MSR_GLIU1 + 0x24) /* DMM */ +#define GLIU1_P2D_BM_3 (MSR_GLIU1 + 0x23) /* SMM */ +#define GLIU1_P2D_BM_4 (MSR_GLIU1 + 0x24) /* DMM */ #define GLIU1_P2D_BM_5 (MSR_GLIU1 + 0x25) #define GLIU1_P2D_BM_6 (MSR_GLIU1 + 0x26) #define GLIU1_P2D_BM_7 (MSR_GLIU1 + 0x27) #define GLIU1_P2D_BM_8 (MSR_GLIU1 + 0x28) -#define GLIU1_P2D_R_0 (MSR_GLIU1 + 0x29) /* SYSMEM */ +#define GLIU1_P2D_R_0 (MSR_GLIU1 + 0x29) /* SYSMEM */ #define GLIU1_P2D_R_1 (MSR_GLIU1 + 0x2A) #define GLIU1_P2D_R_2 (MSR_GLIU1 + 0x2B) #define GLIU1_P2D_R_3 (MSR_GLIU1 + 0x2C) -#define GLIU1_P2D_SC_0 (MSR_GLIU1 + 0x2D) /* SHADOW */ +#define GLIU1_P2D_SC_0 (MSR_GLIU1 + 0x2D) /* SHADOW */ #define GLIU1_IOD_BM_0 (MSR_GLIU1 + 0xE0) #define GLIU1_IOD_BM_1 (MSR_GLIU1 + 0xE1) #define GLIU1_IOD_BM_2 (MSR_GLIU1 + 0xE2) -#define GLIU1_IOD_SC_0 (MSR_GLIU1 + 0xE3) /* FooGlue F0 for FPU */ +#define GLIU1_IOD_SC_0 (MSR_GLIU1 + 0xE3) /* FooGlue F0 for FPU */ #define GLIU1_IOD_SC_1 (MSR_GLIU1 + 0xE4) #define GLIU1_IOD_SC_2 (MSR_GLIU1 + 0xE5) #define GLIU1_IOD_SC_3 (MSR_GLIU1 + 0xE6) @@ -483,21 +495,22 @@ #define GLIU1_IOD_SC_5 (MSR_GLIU1 + 0xE8) /* definitions that are "once you are mostly up, start VSA" type things */ -#define SMM_OFFSET 0x40400000 -#define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */ -#define DMM_OFFSET 0x0C0000000 -#define DMM_SIZE 128 -#define FB_OFFSET 0x41000000 -#define PCI_MEM_TOP 0x0EFFFFFFF /* Top of PCI mem allocation region */ -#define PCI_IO_TOP 0x0EFFF /* Top of PCI I/O allocation region */ -#define END_OPTIONROM_SPACE 0x0DFFF /* E0000 is reserved for SystemROMs */ - -#define MDD_SMBUS 0x06000 /* SMBUS IO location */ -#define MDD_GPIO 0x06100 /* GPIO & ICF IO location */ -#define MDD_MFGPT 0x06200 /* General Purpose Timers IO location */ -#define MDD_IRQ_MAPPER 0x06300 /* IRQ Mapper */ -#define ACPI_BASE 0x09C00 /* ACPI Base */ -#define MDD_PM 0x09D00 /* Power Management Logic - placed at the end of ACPI */ +#define SMM_OFFSET 0x40400000 +#define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */ +#define DMM_OFFSET 0x0C0000000 +#define DMM_SIZE 128 +#define FB_OFFSET 0x41000000 +#define PCI_MEM_TOP 0x0EFFFFFFF /* Top of PCI mem allocation region */ +#define PCI_IO_TOP 0x0EFFF /* Top of PCI I/O allocation region */ +#define END_OPTIONROM_SPACE 0x0DFFF /* E0000 is reserved for SystemROMs */ + +#define MDD_SMBUS 0x06000 /* SMBUS IO location */ +#define MDD_GPIO 0x06100 /* GPIO & ICF IO location */ +#define MDD_MFGPT 0x06200 /* General Purpose Timers IO location */ +#define MDD_IRQ_MAPPER 0x06300 /* IRQ Mapper */ +#define ACPI_BASE 0x09C00 /* ACPI Base */ +/* Power Management Logic - placed at the end of ACPI */ +#define MDD_PM 0x09D00 #define CS5535_IDSEL 0x02000000 /* IDSEL = AD25, device #15 */ #define CHIPSET_DEV_NUM 15 diff --git a/src/include/cpu/amd/lxdef.h b/src/include/cpu/amd/lxdef.h index 0d41c3b660..95fa53fe1f 100644 --- a/src/include/cpu/amd/lxdef.h +++ b/src/include/cpu/amd/lxdef.h @@ -21,19 +21,20 @@ #ifndef CPU_AMD_LXDEF_H #define CPU_AMD_LXDEF_H -#define CPU_ID_1_X 0x00000560 /* Stepping ID 1.x CPUbug fix to change it to 5A0*/ -#define CPU_ID_2_0 0x000005A1 -#define CPU_ID_3_0 0x000005A2 - -#define CPU_REV_1_0 0x010 -#define CPU_REV_1_1 0x011 -#define CPU_REV_2_0 0x020 -#define CPU_REV_2_1 0x021 -#define CPU_REV_2_2 0x022 -#define CPU_REV_C_0 0x030 -#define CPU_REV_C_1 0x031 -#define CPU_REV_C_2 0x032 /* 3.2 part was never produced ...*/ -#define CPU_REV_C_3 0x033 +/* Stepping ID 1.x CPUbug fix to change it to 5A0*/ +#define CPU_ID_1_X 0x00000560 +#define CPU_ID_2_0 0x000005A1 +#define CPU_ID_3_0 0x000005A2 + +#define CPU_REV_1_0 0x010 +#define CPU_REV_1_1 0x011 +#define CPU_REV_2_0 0x020 +#define CPU_REV_2_1 0x021 +#define CPU_REV_2_2 0x022 +#define CPU_REV_C_0 0x030 +#define CPU_REV_C_1 0x031 +#define CPU_REV_C_2 0x032 /* 3.2 part was never produced ...*/ +#define CPU_REV_C_3 0x033 /* MSR routing as follows*/ @@ -59,19 +60,23 @@ #define GL1_AES 6 -#define MSR_GLIU0 ((GL0_GLIU0 << 29) + (1 << 28)) /* 1000xxxx, To get on GeodeLink one bit has to be set */ +/* 1000xxxx, To get on GeodeLink one bit has to be set */ +#define MSR_GLIU0 ((GL0_GLIU0 << 29) + (1 << 28)) #define MSR_MC (GL0_MC << 29) /* 2000xxxx */ #define MSR_GLIU1 (GL0_GLIU1 << 29) /* 4000xxxx */ -#define MSR_CPU (GL0_CPU << 29) /* 0000xxxx this is not used for BIOS since code executing on CPU doesn't need to be routed*/ +/* 0000xxxx this is not used for BIOS since code executing on CPU doesn't + * need to be routed + */ +#define MSR_CPU (GL0_CPU << 29) #define MSR_VG (GL0_VG << 29) /* 8000xxxx */ #define MSR_GP (GL0_GP << 29) /* A000xxxx */ -#define MSR_DF ((GL1_DF << 26) + MSR_GLIU1) /* 4800xxxx */ -#define MSR_GLCP ((GL1_GLCP << 26) + MSR_GLIU1) /* 4C00xxxx */ -#define MSR_PCI ((GL1_PCI << 26) + MSR_GLIU1) /* 5000xxxx */ -#define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1) /* 5400xxxx */ -#define MSR_AES ((GL1_AES << 26) + MSR_GLIU1) /* 5800xxxx */ -#define MSR_FG MSR_GLCP +#define MSR_DF ((GL1_DF << 26) + MSR_GLIU1) /* 4800xxxx */ +#define MSR_GLCP ((GL1_GLCP << 26) + MSR_GLIU1) /* 4C00xxxx */ +#define MSR_PCI ((GL1_PCI << 26) + MSR_GLIU1) /* 5000xxxx */ +#define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1) /* 5400xxxx */ +#define MSR_AES ((GL1_AES << 26) + MSR_GLIU1) /* 5800xxxx */ +#define MSR_FG MSR_GLCP /*GeodeLink Interface Unit 0 (GLIU0) port0*/ @@ -168,9 +173,9 @@ #define CPU_GLD_MSR_DIAG 0x2005 #define DIAG_SEL1_MODE_SHIFT 16 -#define DIAG_SEL1_SET (1 << 31) +#define DIAG_SEL1_SET (1 << 31) #define DIAG_SEL0__MODE_SHIFT 0 -#define DIAG_SET0_SET (1 << 15) +#define DIAG_SET0_SET (1 << 15) #define CPU_PF_CONF 0x1100 #define RETURN_STACK_ENABLE_SET (1 << 4) @@ -207,13 +212,13 @@ #define IM_CONFIG_LOWER_ICD_SET (1 << 8) #define IM_CONFIG_LOWER_EBE_SET (1 << 10) #define IM_CONFIG_LOWER_ABSE_SET (1 << 11) -#define IM_CONFIG_LOWER_QWT_SET (1 << 20) +#define IM_CONFIG_LOWER_QWT_SET (1 << 20) #define CPU_IC_INDEX 0x1710 -#define CPU_IC_DATA 0x1711 -#define CPU_IC_TAG 0x1712 +#define CPU_IC_DATA 0x1711 +#define CPU_IC_TAG 0x1712 #define CPU_IC_TAG_I 0x1713 #define CPU_ITB_INDEX 0x1720 -#define CPU_ITB_LRU 0x1721 +#define CPU_ITB_LRU 0x1721 #define CPU_ITB_ENTRY 0x1722 #define CPU_ITB_ENTRY_I 0x1723 #define CPU_IM_BIST_TAG 0x1730 @@ -313,7 +318,7 @@ #define CPU_BC_MSS_ARRAY_CTL2 0x1983 #define CPU_FPU_MSR_MODE 0x1A00 -#define FPU_IE_SET (1 << 0) +#define FPU_IE_SET (1 << 0) #define CPU_FP_UROM_BIST 0x1A03 @@ -386,13 +391,15 @@ #define RSTPLL_UPPER_CPUMULT_SHIFT 1 #define RSTPLL_UPPER_CPUDIV_SHIFT 0 #define RSTPLL_LOWER_SWFLAGS_SHIFT 26 -#define RSTPLL_LOWER_SWFLAGS_MASK (0x03F << RSTPLL_LOWER_SWFLAGS_SHIFT) +#define RSTPLL_LOWER_SWFLAGS_MASK \ + (0x03F << RSTPLL_LOWER_SWFLAGS_SHIFT) #define RSTPPL_LOWER_HOLD_COUNT_SHIFT 16 #define RSTPPL_LOWER_COREBYPASS_SHIFT 12 #define RSTPPL_LOWER_GLBYPASS_SHIFT 11 #define RSTPPL_LOWER_PCISPEED_SHIFT 7 #define RSTPPL_LOWER_BOOTSTRAP_SHIFT 1 -#define RSTPLL_LOWER_BOOTSTRAP_MASK (0x07F << RSTPLL_LOWER_BOOTSTRAP_SHIFT) +#define RSTPLL_LOWER_BOOTSTRAP_MASK \ + (0x07F << RSTPLL_LOWER_BOOTSTRAP_SHIFT) #define RSTPPL_LOWER_GLLOCK_SET (1 << 25) #define RSTPPL_LOWER_CORELOCK_SET (1 << 24) @@ -489,13 +496,13 @@ #define GLPCI_ExtMSR (MSR_PCI + 0x201E) #define GLPCI_SPARE (MSR_PCI + 0x201F) -#define GLPCI_SPARE_LOWER_AILTO_SET (1<<6) -#define GLPCI_SPARE_LOWER_PPD_SET (1<<5) -#define GLPCI_SPARE_LOWER_PPC_SET (1<<4) -#define GLPCI_SPARE_LOWER_MPC_SET (1<<3) -#define GLPCI_SPARE_LOWER_MME_SET (1<<2) -#define GLPCI_SPARE_LOWER_NSE_SET (1<<1) -#define GLPCI_SPARE_LOWER_SUPO_SET (1<<0) +#define GLPCI_SPARE_LOWER_AILTO_SET (1<<6) +#define GLPCI_SPARE_LOWER_PPD_SET (1<<5) +#define GLPCI_SPARE_LOWER_PPC_SET (1<<4) +#define GLPCI_SPARE_LOWER_MPC_SET (1<<3) +#define GLPCI_SPARE_LOWER_MME_SET (1<<2) +#define GLPCI_SPARE_LOWER_NSE_SET (1<<1) +#define GLPCI_SPARE_LOWER_SUPO_SET (1<<0) @@ -522,15 +529,23 @@ #define MAX_COL_ADDR 17 /* GLIU typedefs */ -#define BM 1 /* Base Mask - map power of 2 size aligned region*/ +/* Base Mask - map power of 2 size aligned region*/ +#define BM 1 #define BMO 2 /* BM with an offset*/ #define R 3 /* Range - 4k range minimum*/ #define RO 4 /* R with offset*/ -#define SC 5 /* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R*/ +/* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R*/ +#define SC 5 #define BMIO 6 /* Base Mask IO*/ #define SCIO 7 /* Swiss 0xCeese IO*/ -#define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independent of CPU*/ -#define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independent of CPU*/ +/* Special marker for Shadow SC descriptors so setShadow proc is independent + * of CPU + */ +#define SC_SHADOW 8 +/* Special marker for SYSMEM R descriptors so GLIUInit proc is independent + * of CPU + */ +#define R_SYSMEM 9 #define BMO_SMM 10 /* Special marker for SMM*/ #define BM_SMM 11 /* Special marker for SMM*/ #define BMO_DMM 12 /* Special marker for DMM*/ @@ -566,7 +581,8 @@ #define GLIU0_P2D_RO_1 (MSR_GLIU0 + 0x2A) #define GLIU0_P2D_RO_2 (MSR_GLIU0 + 0x2B) -#define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC*/ +/* SCO should only be SC*/ +#define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) #define GLIU0_IOD_BM_0 (MSR_GLIU0 + 0xE0) #define GLIU0_IOD_BM_1 (MSR_GLIU0 + 0xE1) @@ -612,12 +628,13 @@ #define GLIU1_IOD_SC_1 (MSR_GLIU1 + 0xE4) #define GLIU1_IOD_SC_2 (MSR_GLIU1 + 0xE5) #define GLIU1_IOD_SC_3 (MSR_GLIU1 + 0xE6) -#define MSR_GLIU1_FPU_TRAP (GLIU1_IOD_SC_0) /* FooGlue F0 for FPU*/ +/* FooGlue F0 for FPU*/ +#define MSR_GLIU1_FPU_TRAP (GLIU1_IOD_SC_0) /* ------------------------ */ #define SMM_OFFSET 0x80400000 /* above 2GB */ -#define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */ +#define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */ /* DRAM_TERMINATED affects how the DELAY register is set. */ #define DRAM_TERMINATED 'T' diff --git a/src/include/cpu/amd/model_fxx_rev.h b/src/include/cpu/amd/model_fxx_rev.h index 210a65227e..7640f6711a 100644 --- a/src/include/cpu/amd/model_fxx_rev.h +++ b/src/include/cpu/amd/model_fxx_rev.h @@ -77,7 +77,8 @@ static inline int is_e0_later_in_bsp(int nodeid) if (nodeid == 0) return !is_cpu_pre_e0(); - // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0 + // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 + // always 0 pci_devfn_t dev; dev = PCI_DEV(0, 0x18+nodeid, 2); val_old = pci_read_config32(dev, 0x80); diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index 31af3e6e92..614c576d03 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -2,7 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, + * Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index 8099a3d1fe..b65c23b83a 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -53,7 +53,8 @@ static inline __attribute__((always_inline)) msr_t rdmsr_amd(unsigned int index) return result; } -static inline __attribute__((always_inline)) void wrmsr_amd(unsigned int index, msr_t msr) +static inline __attribute__((always_inline)) void wrmsr_amd(unsigned int index, + msr_t msr) { __asm__ __volatile__ ( "wrmsr" diff --git a/src/include/cpu/amd/powernow.h b/src/include/cpu/amd/powernow.h index 63968151b0..77df7b031e 100644 --- a/src/include/cpu/amd/powernow.h +++ b/src/include/cpu/amd/powernow.h @@ -2,7 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2009 Rudolf Marek <r.marek@assembler.cz> - * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, + * Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/cpu/intel/l2_cache.h b/src/include/cpu/intel/l2_cache.h index 587e43369f..35059ff74f 100644 --- a/src/include/cpu/intel/l2_cache.h +++ b/src/include/cpu/intel/l2_cache.h @@ -83,10 +83,12 @@ #define L2CMD_MESI_I 0 extern int calculate_l2_latency(void); -extern int signal_l2(u32 address_low, u32 data_high, u32 data_low, int way, u8 command); +extern int signal_l2(u32 address_low, u32 data_high, u32 data_low, int way, + u8 command); extern int read_l2(u32 address); extern int write_l2(u32 address, u32 data); -extern int test_l2_address_alias(u32 address1, u32 address2, u32 data_high, u32 data_low); +extern int test_l2_address_alias(u32 address1, u32 address2, u32 data_high, + u32 data_low); extern int calculate_l2_cache_size(void); extern int calculate_l2_physical_address_range(void); extern int set_l2_ecc(void); diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index f965bae8c7..6f3cbdb2c1 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -13,12 +13,14 @@ # define NEED_LAPIC 0 #endif -static inline __attribute__((always_inline)) unsigned long lapic_read(unsigned long reg) +static inline __attribute__((always_inline)) unsigned long lapic_read( + unsigned long reg) { return *((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg)); } -static inline __attribute__((always_inline)) void lapic_write(unsigned long reg, unsigned long v) +static inline __attribute__((always_inline)) void lapic_write(unsigned long reg, + unsigned long v) { *((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg)) = v; } @@ -67,7 +69,8 @@ void stop_this_cpu(void); #if !defined(__PRE_RAM__) -#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), sizeof(*(ptr)))) +#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \ + sizeof(*(ptr)))) struct __xchg_dummy { unsigned long a[100]; }; #define __xg(x) ((struct __xchg_dummy *)(x)) @@ -77,7 +80,8 @@ struct __xchg_dummy { unsigned long a[100]; }; * Note 2: xchg has side effect, so that attribute volatile is necessary, * but generally the primitive is invalid, *ptr is output argument. --ANK */ -static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size) +static inline unsigned long __xchg(unsigned long x, volatile void *ptr, + int size) { switch (size) { case 1: diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 1175f3b1ba..8070000322 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -37,7 +37,8 @@ static inline __attribute__((always_inline)) msr_t rdmsr(unsigned int index) return soc_msr_read(index); } -static inline __attribute__((always_inline)) void wrmsr(unsigned int index, msr_t msr) +static inline __attribute__((always_inline)) void wrmsr(unsigned int index, + msr_t msr) { soc_msr_write(index, msr); } @@ -64,7 +65,8 @@ static inline __attribute__((always_inline)) msr_t rdmsr(unsigned int index) return result; } -static inline __attribute__((always_inline)) void wrmsr(unsigned int index, msr_t msr) +static inline __attribute__((always_inline)) void wrmsr(unsigned int index, + msr_t msr) { __asm__ __volatile__ ( "wrmsr" diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 99715ed4e6..36b5c712d9 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -147,7 +147,8 @@ static inline unsigned int fls(unsigned int x) # define CACHE_ROM_SIZE CONFIG_ROM_SIZE # else # define CACHE_ROM_SIZE _ALIGN_UP_POW2(CONFIG_ROM_SIZE) -# if (CACHE_ROM_SIZE < CONFIG_ROM_SIZE) || (CACHE_ROM_SIZE >= (2 * CONFIG_ROM_SIZE)) +# if (CACHE_ROM_SIZE < CONFIG_ROM_SIZE) || (CACHE_ROM_SIZE >= \ + (2 * CONFIG_ROM_SIZE)) # error "CACHE_ROM_SIZE is not optimal." # endif # endif diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 48c4c0ba01..1892119d53 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -474,8 +474,10 @@ void northbridge_smi_handler(void); void southbridge_smi_handler(void); #else void cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save); -void northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); -void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); +void northbridge_smi_handler(unsigned int node, + smm_state_save_area_t *state_save); +void southbridge_smi_handler(unsigned int node, + smm_state_save_area_t *state_save); #endif /* CONFIG_SMM_TSEG */ void mainboard_smi_gpi(u32 gpi_sts); int mainboard_smi_apmc(u8 data); diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h index 2ca881cb13..53aad97175 100644 --- a/src/include/device/azalia_device.h +++ b/src/include/device/azalia_device.h @@ -33,14 +33,19 @@ extern const u32 cim_verb_data_size; extern const u32 pc_beep_verbs[]; extern const u32 pc_beep_verbs_size; -#define AZALIA_ARRAY_SIZES const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs); \ +#define AZALIA_ARRAY_SIZES const u32 pc_beep_verbs_size = \ + ARRAY_SIZE(pc_beep_verbs); \ const u32 cim_verb_data_size = sizeof(cim_verb_data) -#define AZALIA_PIN_CFG(codec, pin, val) \ - (((codec) << 28) | ((pin) << 20) | (0x71c << 8) | ((val) & 0xff)), \ - (((codec) << 28) | ((pin) << 20) | (0x71d << 8) | (((val) >> 8) & 0xff)), \ - (((codec) << 28) | ((pin) << 20) | (0x71e << 8) | (((val) >> 16) & 0xff)), \ - (((codec) << 28) | ((pin) << 20) | (0x71f << 8) | (((val) >> 24) & 0xff)) +#define AZALIA_PIN_CFG(codec, pin, val) \ + (((codec) << 28) | ((pin) << 20) | (0x71c << 8) \ + | ((val) & 0xff)), \ + (((codec) << 28) | ((pin) << 20) | (0x71d << 8) \ + | (((val) >> 8) & 0xff)), \ + (((codec) << 28) | ((pin) << 20) | (0x71e << 8) \ + | (((val) >> 16) & 0xff)), \ + (((codec) << 28) | ((pin) << 20) | (0x71f << 8) \ + | (((val) >> 24) & 0xff)) #define AZALIA_SUBVENDOR(codec, val) \ (((codec) << 28) | (0x01720 << 8) | ((val) & 0xff)), \ diff --git a/src/include/device/device.h b/src/include/device/device.h index d3efdd2303..bb0d0ca8b8 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -54,11 +54,13 @@ struct device_operations { void (*set_link)(device_t dev, unsigned int link); void (*reset_bus)(struct bus *bus); #if CONFIG_GENERATE_SMBIOS_TABLES - int (*get_smbios_data)(device_t dev, int *handle, unsigned long *current); + int (*get_smbios_data)(device_t dev, int *handle, + unsigned long *current); void (*get_smbios_strings)(device_t dev, struct smbios_type11 *t); #endif #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) - unsigned long (*write_acpi_tables)(device_t dev, unsigned long start, struct acpi_rsdp *rsdp); + unsigned long (*write_acpi_tables)(device_t dev, unsigned long start, + struct acpi_rsdp *rsdp); void (*acpi_fill_ssdt_generator)(device_t dev); void (*acpi_inject_dsdt_generator)(device_t dev); const char *(*acpi_name)(device_t dev); @@ -84,7 +86,7 @@ struct bus { ROMSTAGE_CONST struct device *dev; /* This bridge device */ ROMSTAGE_CONST struct device *children; /* devices behind this bridge */ - ROMSTAGE_CONST struct bus *next; /* The next bridge on this device */ + ROMSTAGE_CONST struct bus *next; /* The next bridge on this device */ unsigned int bridge_ctrl; /* Bridge control register */ uint16_t bridge_cmd; /* Bridge command register */ unsigned char link_num; /* The index of this link */ @@ -126,7 +128,7 @@ struct device { unsigned int class; /* 3 bytes: (base, sub, prog-if) */ unsigned int hdr_type; /* PCI header type */ unsigned int enabled : 1; /* set if we should enable the device */ - unsigned int initialized : 1; /* set if we have initialized the device */ + unsigned int initialized : 1; /* 1 if we have initialized the device */ unsigned int on_mainboard : 1; struct pci_irq_info pci_irq_info[4]; u8 command; @@ -205,7 +207,8 @@ device_t dev_find_lapic(unsigned int apic_id); int dev_count_cpu(void); device_t add_cpu_device(struct bus *cpu_bus, unsigned int apic_id, int enabled); -void set_cpu_topology(device_t cpu, unsigned int node, unsigned int package, unsigned int core, unsigned int thread); +void set_cpu_topology(device_t cpu, unsigned int node, unsigned int package, + unsigned int core, unsigned int thread); #define amd_cpu_topology(cpu, node, core) \ set_cpu_topology(cpu, node, 0, core, 0) @@ -252,7 +255,8 @@ void scan_lpc_bus(device_t bus); fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE) #define reserved_ram_resource(dev, idx, basek, sizek) \ - fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE | IORESOURCE_RESERVE) + fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE \ + | IORESOURCE_RESERVE) #define bad_ram_resource(dev, idx, basek, sizek) \ reserved_ram_resource((dev), (idx), (basek), (sizek)) @@ -271,7 +275,7 @@ u32 find_pci_tolm(struct bus *bus); ROMSTAGE_CONST struct device *dev_find_slot(unsigned int bus, unsigned int devfn); ROMSTAGE_CONST struct device *dev_find_next_pci_device( - ROMSTAGE_CONST struct device *previous_dev); + ROMSTAGE_CONST struct device *previous_dev); ROMSTAGE_CONST struct device *dev_find_slot_on_smbus(unsigned int bus, unsigned int addr); ROMSTAGE_CONST struct device *dev_find_slot_pnp(u16 port, u16 device); diff --git a/src/include/device/hypertransport_def.h b/src/include/device/hypertransport_def.h index 8af94d94ac..4b340e862e 100644 --- a/src/include/device/hypertransport_def.h +++ b/src/include/device/hypertransport_def.h @@ -21,8 +21,10 @@ static inline bool offset_unit_id(bool is_sb_ht_chain) { - bool need_offset = (CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20); - return need_offset && (!CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY || is_sb_ht_chain); + bool need_offset = (CONFIG_HT_CHAIN_UNITID_BASE != 1) + || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20); + return need_offset && (!CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY + || is_sb_ht_chain); } #endif /* DEVICE_HYPERTRANSPORT_DEF_H */ diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 952f6e3d39..4f6dfbc590 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -42,9 +42,12 @@ struct pci_bus_operations { uint8_t (*read8)(struct bus *pbus, int bus, int devfn, int where); uint16_t (*read16)(struct bus *pbus, int bus, int devfn, int where); uint32_t (*read32)(struct bus *pbus, int bus, int devfn, int where); - void (*write8)(struct bus *pbus, int bus, int devfn, int where, uint8_t val); - void (*write16)(struct bus *pbus, int bus, int devfn, int where, uint16_t val); - void (*write32)(struct bus *pbus, int bus, int devfn, int where, uint32_t val); + void (*write8)(struct bus *pbus, int bus, int devfn, int where, + uint8_t val); + void (*write16)(struct bus *pbus, int bus, int devfn, int where, + uint16_t val); + void (*write32)(struct bus *pbus, int bus, int devfn, int where, + uint32_t val); }; struct pci_driver { diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index a1236eff2d..1674ee1e49 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -23,7 +23,8 @@ #define PCI_STATUS 0x06 /* 16 bits */ #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ -#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ +/* Support User Definable Features [obsolete] */ +#define PCI_STATUS_UDF 0x40 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ @@ -82,11 +83,13 @@ #define PCI_CARDBUS_CIS 0x28 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c #define PCI_SUBSYSTEM_ID 0x2e -#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ +/* Bits 31..11 are address, 10..1 reserved */ +#define PCI_ROM_ADDRESS 0x30 #define PCI_ROM_ADDRESS_ENABLE 0x01 #define PCI_ROM_ADDRESS_MASK (~0x7ffUL) -#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ +/* Offset of first capability list entry */ +#define PCI_CAPABILITY_LIST 0x34 /* 0x35-0x3b are reserved */ #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ @@ -97,15 +100,18 @@ /* Header type 1 (PCI-to-PCI bridges) */ #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ -#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ -#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ +/* Highest bus number behind the bridge */ +#define PCI_SUBORDINATE_BUS 0x1a +/* Latency timer for secondary interface */ +#define PCI_SEC_LATENCY_TIMER 0x1b #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ #define PCI_IO_LIMIT 0x1d #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */ #define PCI_IO_RANGE_TYPE_16 0x00 #define PCI_IO_RANGE_TYPE_32 0x01 #define PCI_IO_RANGE_MASK ~0x0f -#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ +/* Secondary status register, only bit 14 used */ +#define PCI_SEC_STATUS 0x1e #define PCI_MEMORY_BASE 0x20 /* Memory range behind */ #define PCI_MEMORY_LIMIT 0x22 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f @@ -116,22 +122,26 @@ #define PCI_PREF_RANGE_TYPE_32 0x00 #define PCI_PREF_RANGE_TYPE_64 0x01 #define PCI_PREF_RANGE_MASK ~0x0f -#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ +/* Upper half of prefetchable memory range */ +#define PCI_PREF_BASE_UPPER32 0x28 #define PCI_PREF_LIMIT_UPPER32 0x2c #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ #define PCI_IO_LIMIT_UPPER16 0x32 /* 0x34 same as for htype 0 */ /* 0x35-0x3b is reserved */ -#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ +/* Same as PCI_ROM_ADDRESS, but for htype 1 */ +#define PCI_ROM_ADDRESS1 0x38 /* 0x3c-0x3d are same as for htype 0 */ #define PCI_BRIDGE_CONTROL 0x3e -#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ +/* Enable parity detection on secondary interface */ +#define PCI_BRIDGE_CTL_PARITY 0x01 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ -#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ +/* Fast Back2Back enabled on secondary interface */ +#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Header type 2 (CardBus bridges) */ #define PCI_CB_CAPABILITY_LIST 0x14 @@ -156,19 +166,23 @@ #define PCI_CB_IO_RANGE_MASK ~0x03 /* 0x3c-0x3d are same as for htype 0 */ #define PCI_CB_BRIDGE_CONTROL 0x3e -#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ +/* Similar to standard bridge control register */ +#define PCI_CB_BRIDGE_CTL_PARITY 0x01 #define PCI_CB_BRIDGE_CTL_SERR 0x02 #define PCI_CB_BRIDGE_CTL_ISA 0x04 #define PCI_CB_BRIDGE_CTL_VGA 0x08 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ -#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ -#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ +/* Enable interrupt for 16-bit cards */ +#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 +/* Prefetch enable for both memory regions */ +#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 #define PCI_CB_SUBSYSTEM_ID 0x42 -#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ +/* 16-bit PC Card legacy mode base address (ExCa) */ +#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 0x48-0x7f reserved */ /* Capability lists */ @@ -223,7 +237,8 @@ #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ -#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ +/* Bus power/clock control enable (??) */ +#define PCI_PM_BPCC_ENABLE 0x80 #define PCI_PM_DATA_REGISTER 7 /* (??) */ #define PCI_PM_SIZEOF 8 @@ -232,7 +247,8 @@ #define PCI_AGP_VERSION 2 /* BCD version number */ #define PCI_AGP_RFU 3 /* Rest of capability flags */ #define PCI_AGP_STATUS 4 /* Status register */ -#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ +/* Maximum number of requests - 1 */ +#define PCI_AGP_STATUS_RQ_MASK 0xff000000 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ @@ -240,10 +256,13 @@ #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ #define PCI_AGP_COMMAND 8 /* Control register */ -#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ +/* Master: Maximum number of requests */ +#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ -#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ -#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ +/* Allow processing of AGP transactions */ +#define PCI_AGP_COMMAND_AGP 0x0100 +/* Allow processing of 64-bit addresses */ +#define PCI_AGP_COMMAND_64BIT 0x0020 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */ @@ -253,7 +272,8 @@ /* Slot Identification */ #define PCI_SID_ESR 2 /* Expansion Slot Register */ -#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ +/* Number of expansion slots available */ +#define PCI_SID_ESR_NSLOTS 0x1f #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ @@ -266,7 +286,8 @@ #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */ #define PCI_MSI_RFU 3 /* Rest of capability flags */ #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ -#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ +/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ +#define PCI_MSI_ADDRESS_HI 8 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ #define PCI_MSI_MASK_BIT 16 /* Mask bits register */ @@ -296,24 +317,30 @@ #define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */ #define PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */ #define PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */ -#define PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */ +/* Unexpected Split Completion */ +#define PCI_X_STATUS_UNX_SPL 0x00080000 #define PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity */ -#define PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */ -#define PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */ -#define PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */ -#define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */ +/* Designed Max Memory Read Count */ +#define PCI_X_STATUS_MAX_READ 0x00600000 +/* Designed Max Cumulative Read Size */ +#define PCI_X_STATUS_MAX_SPLIT 0x03800000 +/* Rcvd Split Completion Error Msg */ +#define PCI_X_STATUS_SPL_ERR 0x20000000 #define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */ #define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */ /* PCI-X bridge registers */ #define PCI_X_SEC_STATUS 2 /* Secondary status */ -#define PCI_X_SSTATUS_64BIT 0x0001 /* The bus behind the bridge is 64bits wide */ -#define PCI_X_SSTATUS_133MHZ 0x0002 /* The bus behind the bridge is 133Mhz Capable */ +/* The bus behind the bridge is 64bits wide */ +#define PCI_X_SSTATUS_64BIT 0x0001 +/* The bus behind the bridge is 133Mhz Capable */ +#define PCI_X_SSTATUS_133MHZ 0x0002 #define PCI_X_SSTATUS_SPL_DISC 0x0004 /* Split Completion Discarded */ #define PCI_X_SSTATUS_UNX_SPL 0x0008 /* Unexpected Split Completion */ #define PCI_X_SSTATUS_SPL_OVR 0x0010 /* Split Completion Overrun */ #define PCI_X_SSTATUS_SPL_DLY 0x0020 /* Split Completion Delayed */ -#define PCI_X_SSTATUS_MFREQ(x) (((x) & 0x03c0) >> 6) /* PCI-X mode and frequency */ +/* PCI-X mode and frequency */ +#define PCI_X_SSTATUS_MFREQ(x) (((x) & 0x03c0) >> 6) #define PCI_X_SSTATUS_CONVENTIONAL_PCI 0x0 #define PCI_X_SSTATUS_MODE1_66MHZ 0x1 #define PCI_X_SSTATUS_MODE1_100MHZ 0x2 @@ -325,8 +352,10 @@ #define PCI_X_SSTATUS_MODE2_533MHZ_REF_100MHZ 0xe #define PCI_X_SSTATUS_MODE2_533MHZ_REF_133MHZ 0xf #define PCI_X_SSTATUS_VERSION(x) (((x) >> 12) & 3) /* Version */ -#define PCI_X_SSTATUS_266MHZ 0x4000 /* The bus behind the bridge is 266Mhz Capable */ -#define PCI_X_SSTAUTS_533MHZ 0x8000 /* The bus behind the bridge is 533Mhz Capable */ +/* The bus behind the bridge is 266Mhz Capable */ +#define PCI_X_SSTATUS_266MHZ 0x4000 +/* The bus behind the bridge is 533Mhz Capable */ +#define PCI_X_SSTAUTS_533MHZ 0x8000 /* PCI Express capability registers */ diff --git a/src/include/device/pci_ehci.h b/src/include/device/pci_ehci.h index 4a89a60852..1eb3cd025a 100644 --- a/src/include/device/pci_ehci.h +++ b/src/include/device/pci_ehci.h @@ -21,7 +21,7 @@ #include <device/device.h> #define EHCI_BAR_INDEX 0x10 -#define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */ +#define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx); u8 *pci_ehci_base_regs(pci_devfn_t dev); diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index 7266a8f34e..c5ace4c788 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -35,7 +35,8 @@ struct pci_data { }; struct rom_header *pci_rom_probe(struct device *dev); -struct rom_header *pci_rom_load(struct device *dev, struct rom_header *rom_header); +struct rom_header *pci_rom_load(struct device *dev, + struct rom_header *rom_header); unsigned long pci_rom_write_acpi_tables(struct device *device, diff --git a/src/include/device/resource.h b/src/include/device/resource.h index 7791e70009..d794fb21e7 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -11,7 +11,8 @@ #define IORESOURCE_IRQ 0x00000400 #define IORESOURCE_DRQ 0x00000800 -#define IORESOURCE_TYPE_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_IRQ | IORESOURCE_DRQ) +#define IORESOURCE_TYPE_MASK (IORESOURCE_IO | IORESOURCE_MEM \ + | IORESOURCE_IRQ | IORESOURCE_DRQ) #define IORESOURCE_PREFETCH 0x00001000 /* No side effects */ #define IORESOURCE_READONLY 0x00002000 @@ -19,14 +20,18 @@ #define IORESOURCE_RANGELENGTH 0x00008000 #define IORESOURCE_SHADOWABLE 0x00010000 #define IORESOURCE_BUS_HAS_VGA 0x00020000 -#define IORESOURCE_SUBTRACTIVE 0x00040000 /* This resource filters all of the unclaimed transactions - * to the bus below. - */ -#define IORESOURCE_BRIDGE 0x00080000 /* The IO resource has a bus below it. */ -#define IORESOURCE_RESERVE 0x10000000 /* The resource needs to be reserved in the coreboot table */ -#define IORESOURCE_STORED 0x20000000 /* The IO resource assignment has been stored in the device */ -#define IORESOURCE_ASSIGNED 0x40000000 /* An IO resource that has been assigned a value */ -#define IORESOURCE_FIXED 0x80000000 /* An IO resource the allocator must not change */ +/* This resource filters all of the unclaimed transactions to the bus below. */ +#define IORESOURCE_SUBTRACTIVE 0x00040000 +/* The IO resource has a bus below it. */ +#define IORESOURCE_BRIDGE 0x00080000 +/* The resource needs to be reserved in the coreboot table */ +#define IORESOURCE_RESERVE 0x10000000 +/* The IO resource assignment has been stored in the device */ +#define IORESOURCE_STORED 0x20000000 +/* An IO resource that has been assigned a value */ +#define IORESOURCE_ASSIGNED 0x40000000 +/* An IO resource the allocator must not change */ +#define IORESOURCE_FIXED 0x80000000 /* PCI specific resource bits (IORESOURCE_BITS) */ #define IORESOURCE_PCI64 (1<<0) /* 64bit long pci resource */ @@ -62,9 +67,11 @@ extern struct resource *new_resource(struct device *dev, unsigned int index); extern struct resource *find_resource(struct device *dev, unsigned int index); extern resource_t resource_end(struct resource *resource); extern resource_t resource_max(struct resource *resource); -extern void report_resource_stored(struct device *dev, struct resource *resource, const char *comment); +extern void report_resource_stored(struct device *dev, + struct resource *resource, const char *comment); -typedef void (*resource_search_t)(void *gp, struct device *dev, struct resource *res); +typedef void (*resource_search_t)(void *gp, struct device *dev, + struct resource *res); extern void search_bus_resources(struct bus *bus, unsigned long type_mask, unsigned long type, resource_search_t search, void *gp); diff --git a/src/include/ip_checksum.h b/src/include/ip_checksum.h index f6ef560057..f2632e7cae 100644 --- a/src/include/ip_checksum.h +++ b/src/include/ip_checksum.h @@ -1,5 +1,6 @@ #ifndef IP_CHECKSUM_H #define IP_CHECKSUM_H unsigned long compute_ip_checksum(const void *addr, unsigned long length); -unsigned long add_ip_checksums(unsigned long offset, unsigned long sum, unsigned long new); +unsigned long add_ip_checksums(unsigned long offset, unsigned long sum, + unsigned long new); #endif /* IP_CHECKSUM_H */ diff --git a/src/include/nhlt.h b/src/include/nhlt.h index 5b72320f02..f692b9ab69 100644 --- a/src/include/nhlt.h +++ b/src/include/nhlt.h @@ -320,7 +320,8 @@ struct nhlt_dmic_array_config { /* * Microphone array definitions may be found here: - * https://msdn.microsoft.com/en-us/library/windows/hardware/dn613960%28v=vs.85%29.aspx + * https://msdn.microsoft.com/en-us/library/windows/hardware/ + * dn613960%28v=vs.85%29.aspx */ enum { NHLT_MIC_ARRAY_2CH_SMALL = 0xa, diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index be90358b05..ef19a15363 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -40,7 +40,9 @@ /* 2 values for divider stage reset, others for "testing purposes only" */ # define RTC_DIV_RESET1 0x60 # define RTC_DIV_RESET2 0x70 - /* Periodic intr. / Square wave rate select. 0 = none, 1 = 32.8kHz,... 15 = 2Hz */ + /* Periodic intr. / Square wave rate select. 0 = none, + * 1 = 32.8kHz,... 15 = 2Hz + */ # define RTC_RATE_SELECT 0x0F # define RTC_RATE_NONE 0x00 # define RTC_RATE_32786HZ 0x01 @@ -188,7 +190,8 @@ unsigned int read_option_lowlevel(unsigned int start, unsigned int size, #else /* defined(__ROMCC__) */ #include <drivers/pc80/rtc/mc146818rtc_early.c> #endif /* !defined(__ROMCC__) */ -#define read_option(name, default) read_option_lowlevel(CMOS_VSTART_ ##name, CMOS_VLEN_ ##name, (default)) +#define read_option(name, default) read_option_lowlevel(CMOS_VSTART_ ##name, \ + CMOS_VLEN_ ##name, (default)) #if CONFIG_CMOS_POST #if CONFIG_USE_OPTION_TABLE diff --git a/src/include/smbios.h b/src/include/smbios.h index 96d9bea442..5a9ef37286 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -1,7 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, + * Raptor Engineering * Copyright (C) various authors, the coreboot project * * This program is free software; you can redistribute it and/or modify @@ -471,6 +472,7 @@ struct smbios_type127 { u8 eos[2]; } __attribute__((packed)); -void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id, struct smbios_type17 *t); +void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id, + struct smbios_type17 *t); #endif diff --git a/src/include/spd.h b/src/include/spd.h index 0bc7898749..9ada5c3c6d 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -34,64 +34,110 @@ #define _SPD_H_ /* Byte numbers. */ -#define SPD_NUM_MANUFACTURER_BYTES 0 /* Number of bytes used by module manufacturer */ +/* Number of bytes used by module manufacturer */ +#define SPD_NUM_MANUFACTURER_BYTES 0 #define SPD_TOTAL_SPD_MEMORY_SIZE 1 /* Total SPD memory size */ #define SPD_MEMORY_TYPE 2 /* (Fundamental) memory type */ #define SPD_NUM_ROWS 3 /* Number of row address bits */ -#define SPD_NUM_COLUMNS 4 /* Number of column address bits */ -#define SPD_NUM_DIMM_BANKS 5 /* Number of module rows (banks) */ +/* Number of column address bits */ +#define SPD_NUM_COLUMNS 4 +/* Number of module rows (banks) */ +#define SPD_NUM_DIMM_BANKS 5 #define SPD_MODULE_DATA_WIDTH_LSB 6 /* Module data width (LSB) */ #define SPD_MODULE_DATA_WIDTH_MSB 7 /* Module data width (MSB) */ -#define SPD_MODULE_VOLTAGE 8 /* Module interface signal levels */ -#define SPD_MIN_CYCLE_TIME_AT_CAS_MAX 9 /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */ -#define SPD_ACCESS_TIME_FROM_CLOCK 10 /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */ +/* Module interface signal levels */ +#define SPD_MODULE_VOLTAGE 8 +/* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */ +#define SPD_MIN_CYCLE_TIME_AT_CAS_MAX 9 +/* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, + * tCAC) + */ +#define SPD_ACCESS_TIME_FROM_CLOCK 10 #define SPD_DIMM_CONFIG_TYPE 11 /* Module configuration type */ #define SPD_REFRESH 12 /* Refresh rate/type */ #define SPD_PRIMARY_SDRAM_WIDTH 13 /* SDRAM width (primary SDRAM) */ -#define SPD_ERROR_CHECKING_SDRAM_WIDTH 14 /* Error checking SDRAM (data) width */ -#define SPD_MIN_CLOCK_DELAY_B2B_RAND_COLUMN 15 /* SDRAM device attributes, minimum clock delay for back to back random column */ -#define SPD_SUPPORTED_BURST_LENGTHS 16 /* SDRAM device attributes, burst lengths supported */ -#define SPD_NUM_BANKS_PER_SDRAM 17 /* SDRAM device attributes, number of banks on SDRAM device */ -#define SPD_ACCEPTABLE_CAS_LATENCIES 18 /* SDRAM device attributes, CAS latency */ -#define SPD_CS_LATENCY 19 /* SDRAM device attributes, CS latency */ -#define SPD_WE_LATENCY 20 /* SDRAM device attributes, WE latency */ +/* Error checking SDRAM (data) width */ +#define SPD_ERROR_CHECKING_SDRAM_WIDTH 14 +/* SDRAM device attributes, minimum clock delay for back to back random + * column + */ +#define SPD_MIN_CLOCK_DELAY_B2B_RAND_COLUMN 15 +/* SDRAM device attributes, burst lengths supported */ +#define SPD_SUPPORTED_BURST_LENGTHS 16 +/* SDRAM device attributes, number of banks on SDRAM device */ +#define SPD_NUM_BANKS_PER_SDRAM 17 +/* SDRAM device attributes, CAS latency */ +#define SPD_ACCEPTABLE_CAS_LATENCIES 18 +/* SDRAM device attributes, CS latency */ +#define SPD_CS_LATENCY 19 +/* SDRAM device attributes, WE latency */ +#define SPD_WE_LATENCY 20 #define SPD_MODULE_ATTRIBUTES 21 /* SDRAM module attributes */ -#define SPD_DEVICE_ATTRIBUTES_GENERAL 22 /* SDRAM device attributes, general */ -#define SPD_SDRAM_CYCLE_TIME_2ND 23 /* SDRAM cycle time (2nd highest CAS latency) */ -#define SPD_ACCESS_TIME_FROM_CLOCK_2ND 24 /* SDRAM access from clock (2nd highest CAS latency) */ -#define SPD_SDRAM_CYCLE_TIME_3RD 25 /* SDRAM cycle time (3rd highest CAS latency) */ -#define SPD_ACCESS_TIME_FROM_CLOCK_3RD 26 /* SDRAM access from clock (3rd highest CAS latency) */ -#define SPD_MIN_ROW_PRECHARGE_TIME 27 /* Minimum row precharge time (Trp) */ -#define SPD_MIN_ROWACTIVE_TO_ROWACTIVE 28 /* Minimum row active to row active (Trrd) */ -#define SPD_MIN_RAS_TO_CAS_DELAY 29 /* Minimum RAS to CAS delay (Trcd) */ -#define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY 30 /* Minimum RAS pulse width (Tras) */ -#define SPD_DENSITY_OF_EACH_ROW_ON_MODULE 31 /* Density of each row on module */ -#define SPD_CMD_SIGNAL_INPUT_SETUP_TIME 32 /* Command and address signal input setup time */ -#define SPD_CMD_SIGNAL_INPUT_HOLD_TIME 33 /* Command and address signal input hold time */ -#define SPD_DATA_SIGNAL_INPUT_SETUP_TIME 34 /* Data signal input setup time */ +/* SDRAM device attributes, general */ +#define SPD_DEVICE_ATTRIBUTES_GENERAL 22 +/* SDRAM cycle time (2nd highest CAS latency) */ +#define SPD_SDRAM_CYCLE_TIME_2ND 23 +/* SDRAM access from clock (2nd highest CAS latency) */ +#define SPD_ACCESS_TIME_FROM_CLOCK_2ND 24 +/* SDRAM cycle time (3rd highest CAS latency) */ +#define SPD_SDRAM_CYCLE_TIME_3RD 25 +/* SDRAM access from clock (3rd highest CAS latency) */ +#define SPD_ACCESS_TIME_FROM_CLOCK_3RD 26 +/* Minimum row precharge time (Trp) */ +#define SPD_MIN_ROW_PRECHARGE_TIME 27 +/* Minimum row active to row active (Trrd) */ +#define SPD_MIN_ROWACTIVE_TO_ROWACTIVE 28 +/* Minimum RAS to CAS delay (Trcd) */ +#define SPD_MIN_RAS_TO_CAS_DELAY 29 +/* Minimum RAS pulse width (Tras) */ +#define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY 30 +/* Density of each row on module */ +#define SPD_DENSITY_OF_EACH_ROW_ON_MODULE 31 +/* Command and address signal input setup time */ +#define SPD_CMD_SIGNAL_INPUT_SETUP_TIME 32 +/* Command and address signal input hold time */ +#define SPD_CMD_SIGNAL_INPUT_HOLD_TIME 33 +/* Data signal input setup time */ +#define SPD_DATA_SIGNAL_INPUT_SETUP_TIME 34 #define SPD_DATA_SIGNAL_INPUT_HOLD_TIME 35 /* Data signal input hold time */ #define SPD_WRITE_RECOVERY_TIME 36 /* Write recovery time (tWR) */ -#define SPD_INT_WRITE_TO_READ_DELAY 37 /* Internal write to read command delay (tWTR) */ -#define SPD_INT_READ_TO_PRECHARGE_DELAY 38 /* Internal read to precharge command delay (tRTP) */ -#define SPD_MEM_ANALYSIS_PROBE_PARAMS 39 /* Memory analysis probe characteristics */ -#define SPD_BYTE_41_42_EXTENSION 40 /* Extension of byte 41 (tRC) and byte 42 (tRFC) */ -#define SPD_MIN_ACT_TO_ACT_AUTO_REFRESH 41 /* Minimum active to active auto refresh (tRCmin) */ -#define SPD_MIN_AUTO_REFRESH_TO_ACT 42 /* Minimum auto refresh to active/auto refresh (tRFC) */ -#define SPD_MAX_DEVICE_CYCLE_TIME 43 /* Maximum device cycle time (tCKmax) */ -#define SPD_MAX_DQS_DQ_SKEW 44 /* Maximum skew between DQS and DQ (tDQSQ) */ -#define SPD_MAX_READ_DATAHOLD_SKEW 45 /* Maximum read data-hold skew factor (tQHS) */ +/* Internal write to read command delay (tWTR) */ +#define SPD_INT_WRITE_TO_READ_DELAY 37 +/* Internal read to precharge command delay (tRTP) */ +#define SPD_INT_READ_TO_PRECHARGE_DELAY 38 +/* Memory analysis probe characteristics */ +#define SPD_MEM_ANALYSIS_PROBE_PARAMS 39 +/* Extension of byte 41 (tRC) and byte 42 (tRFC) */ +#define SPD_BYTE_41_42_EXTENSION 40 +/* Minimum active to active auto refresh (tRCmin) */ +#define SPD_MIN_ACT_TO_ACT_AUTO_REFRESH 41 +/* Minimum auto refresh to active/auto refresh (tRFC) */ +#define SPD_MIN_AUTO_REFRESH_TO_ACT 42 +/* Maximum device cycle time (tCKmax) */ +#define SPD_MAX_DEVICE_CYCLE_TIME 43 +/* Maximum skew between DQS and DQ (tDQSQ) */ +#define SPD_MAX_DQS_DQ_SKEW 44 +/* Maximum read data-hold skew factor (tQHS) */ +#define SPD_MAX_READ_DATAHOLD_SKEW 45 #define SPD_PLL_RELOCK_TIME 46 /* PLL relock time */ #define SPD_SPD_DATA_REVISION_CODE 62 /* SPD data revision code */ #define SPD_CHECKSUM_FOR_BYTES_0_TO_62 63 /* Checksum for bytes 0-62 */ -#define SPD_MANUFACTURER_JEDEC_ID_CODE 64 /* Manufacturer's JEDEC ID code, per EIA/JEP106 (bytes 64-71) */ +/* Manufacturer's JEDEC ID code, per EIA/JEP106 (bytes 64-71) */ +#define SPD_MANUFACTURER_JEDEC_ID_CODE 64 #define SPD_MANUFACTURING_LOCATION 72 /* Manufacturing location */ -#define SPD_MANUFACTURER_PART_NUMBER 73 /* Manufacturer's part number, in 6-bit ASCII (bytes 73-90) */ +/* Manufacturer's part number, in 6-bit ASCII (bytes 73-90) */ +#define SPD_MANUFACTURER_PART_NUMBER 73 #define SPD_REVISION_CODE 91 /* Revision code (bytes 91-92) */ -#define SPD_MANUFACTURING_DATE 93 /* Manufacturing date (byte 93: year, byte 94: week) */ -#define SPD_ASSEMBLY_SERIAL_NUMBER 95 /* Assembly serial number (bytes 95-98) */ -#define SPD_MANUFACTURER_SPECIFIC_DATA 99 /* Manufacturer specific data (bytes 99-125) */ -#define SPD_INTEL_SPEC_FOR_FREQUENCY 126 /* Intel specification for frequency */ -#define SPD_INTEL_SPEC_100_MHZ 127 /* Intel specification details for 100MHz support */ +/* Manufacturing date (byte 93: year, byte 94: week) */ +#define SPD_MANUFACTURING_DATE 93 +/* Assembly serial number (bytes 95-98) */ +#define SPD_ASSEMBLY_SERIAL_NUMBER 95 +/* Manufacturer specific data (bytes 99-125) */ +#define SPD_MANUFACTURER_SPECIFIC_DATA 99 +/* Intel specification for frequency */ +#define SPD_INTEL_SPEC_FOR_FREQUENCY 126 +/* Intel specification details for 100MHz support */ +#define SPD_INTEL_SPEC_100_MHZ 127 /* DRAM specifications use the following naming conventions for SPD locations */ #define SPD_tRP SPD_MIN_ROW_PRECHARGE_TIME @@ -100,8 +146,10 @@ #define SPD_tRAS SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY #define SPD_BANK_DENSITY SPD_DENSITY_OF_EACH_ROW_ON_MODULE #define SPD_ADDRESS_CMD_HOLD SPD_CMD_SIGNAL_INPUT_HOLD_TIME -#define SPD_tRC 41 /* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */ -#define SPD_tRFC 42 /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */ +/* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */ +#define SPD_tRC 41 +/* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */ +#define SPD_tRFC 42 /* SPD_MEMORY_TYPE values. */ diff --git a/src/include/spd_ddr2.h b/src/include/spd_ddr2.h index d5b2584b6d..848cc5d421 100644 --- a/src/include/spd_ddr2.h +++ b/src/include/spd_ddr2.h @@ -54,7 +54,9 @@ SDRAM device, it could be 0x4, 0x8, so address lines for that would be 2, and 3 */ -/* Number of Ranks bit [2:0], Package (bit4, 1 = stack, 0 = planr), Height bit[7:5] */ +/* Number of Ranks bit [2:0], Package (bit4, 1 = stack, 0 = planr), + * Height bit[7:5] + */ #define SPD_MOD_ATTRIB_RANK 5 #define SPD_MOD_ATTRIB_RANK_NUM_SHIFT 0 #define SPD_MOD_ATTRIB_RANK_NUM_MASK 0x07 @@ -72,9 +74,12 @@ #define SPD_RANK_SIZE_256MB (1<<6) #define SPD_RANK_SIZE_512MB (1<<7) -#define SPD_DATA_WIDTH 6 /* valid value 0, 32, 33, 36, 64, 72, 80, 128, 144, 254, 255 */ -#define SPD_PRI_WIDTH 13 /* Primary SDRAM Width, it could be 0x08 or 0x10 */ -#define SPD_ERR_WIDTH 14 /* Error Checking SDRAM Width, it could be 0x08 or 0x10 */ +/* valid value 0, 32, 33, 36, 64, 72, 80, 128, 144, 254, 255 */ +#define SPD_DATA_WIDTH 6 +/* Primary SDRAM Width, it could be 0x08 or 0x10 */ +#define SPD_PRI_WIDTH 13 +/* Error Checking SDRAM Width, it could be 0x08 or 0x10 */ +#define SPD_ERR_WIDTH 14 #define SPD_CAS_LAT 18 /* SDRAM Device Attributes -- CAS Latency */ #define SPD_CAS_LAT_2 (1<<2) @@ -84,16 +89,25 @@ #define SPD_CAS_LAT_6 (1<<6) #define SPD_CAS_LAT_7 (1<<7) -#define SPD_TRP 27 /* bit [7:2] = 1-63 ns, bit [1:0] 0.25ns+, final value ((val>>2) + (val & 3) * 0.25)ns */ +/* bit [7:2] = 1-63 ns, bit [1:0] 0.25ns+, final value ((val>>2) + * + (val & 3) * 0.25)ns + */ +#define SPD_TRP 27 #define SPD_TRRD 28 #define SPD_TRCD 29 #define SPD_TRAS 30 -#define SPD_TWR 36 /* x */ +#define SPD_TWR 36 /* x */ #define SPD_TWTR 37 /* x */ #define SPD_TRTP 38 /* x */ #define SPD_EX_TRC_TRFC 40 -#define SPD_TRC 41 /* add byte 0x40 bit [3:1] , so final val41+ table[((val40>>1) & 0x7)] ... table[]={0, 0.25, 0.33, 0.5, 0.75, 0, 0}*/ -#define SPD_TRFC 42 /* add byte 0x40 bit [6:4] , so final val42+ table[((val40>>4) & 0x7)] + (val40 & 1)*256*/ +/* add byte 0x40 bit [3:1] , so final val41+ table[((val40>>1) & 0x7)] + * ... table[]={0, 0.25, 0.33, 0.5, 0.75, 0, 0} + */ +#define SPD_TRC 41 +/* add byte 0x40 bit [6:4] , so final val42+ table[((val40>>4) & 0x7)] + * + (val40 & 1)*256 + */ +#define SPD_TRFC 42 #define SPD_TREF 12 diff --git a/src/include/timestamp.h b/src/include/timestamp.h index 7e51d80eb2..58edb52fcb 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -18,7 +18,8 @@ #include <commonlib/timestamp_serialized.h> -#if CONFIG_COLLECT_TIMESTAMPS && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)) +#if CONFIG_COLLECT_TIMESTAMPS && (CONFIG_EARLY_CBMEM_INIT \ + || !defined(__PRE_RAM__)) /* * timestamp_init() needs to be called once for each of these cases: * 1. __PRE_RAM__ (bootblock, romstage, verstage, etc) and diff --git a/src/include/vbe.h b/src/include/vbe.h index 53ea998b86..54dc560699 100644 --- a/src/include/vbe.h +++ b/src/include/vbe.h @@ -19,7 +19,8 @@ typedef struct { u8 display_type; // 0 = NONE, 1 = analog, 2 = digital u16 screen_width; u16 screen_height; - u16 screen_linebytes; // bytes per line in framebuffer, may be more than screen_width + u16 screen_linebytes; // bytes per line in framebuffer, may be more + // than screen_width u8 color_depth; // color depth in bits per pixel u32 framebuffer_address; u8 edid_block_zero[128]; @@ -40,7 +41,8 @@ typedef struct { u16 version; u8 *oem_string_ptr; u32 capabilities; - u16 video_mode_list[256]; // lets hope we never have more than 256 video modes... + u16 video_mode_list[256]; // lets hope we never have more than + // 256 video modes... u16 total_memory; } vbe_info_t; |