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authorjinkun.hong <jinkun.hong@rock-chips.com>2015-03-02 14:10:50 +0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-21 08:16:56 +0200
commit5792e3b71f205446155bb40bea9c52dfe1969d8b (patch)
treefaabb4caa1268bdbcb8886baac04ba1ab4ff5e3c
parentdbdd0661a599b4da53129bb3ed866a5fd3afce7c (diff)
veyron_jerry: support K4B8G1646Q-4GB and H5TC8G63XXX-4GB ddr3
add the K4B8G1646Q-4GB and H5TC8G63XXX-4GB ddr3 inf file, and use ram_id 1110 correspond to K4B8G1646Q-4GB ddr3 use ram_id 1111 correspond to H5TC8G63XXX-4GB ddr3 BUG=None TEST=Boot veyron_jerry normal BRANCH=None Change-Id: I3398516a9f2c2e44c9f5d08d0a3ab6e76b5c6f5f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b8dfc455bb93c2daf567e3b6e39c0a715e44311c Original-Change-Id: I90250cb84eb140f93c4fc655fb3b90584dd515c0 Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/255010 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9826 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/mainboard/google/veyron_jerry/sdram_configs.c4
-rw-r--r--src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-H5TC8G63XXX-4GB.inc77
-rw-r--r--src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-K4B8G1646Q-4GB.inc77
3 files changed, 156 insertions, 2 deletions
diff --git a/src/mainboard/google/veyron_jerry/sdram_configs.c b/src/mainboard/google/veyron_jerry/sdram_configs.c
index 362e950255..a9606c2713 100644
--- a/src/mainboard/google/veyron_jerry/sdram_configs.c
+++ b/src/mainboard/google/veyron_jerry/sdram_configs.c
@@ -39,8 +39,8 @@ static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1101 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1110 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1111 */
+#include "sdram_inf/sdram-ddr3-K4B8G1646Q-4GB.inc" /* ram_code = 1110 */
+#include "sdram_inf/sdram-ddr3-H5TC8G63XXX-4GB.inc" /* ram_code = 1111 */
};
const struct rk3288_sdram_params *get_sdram_config()
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-H5TC8G63XXX-4GB.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-H5TC8G63XXX-4GB.inc
new file mode 100644
index 0000000000..4e89ebf473
--- /dev/null
+++ b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-H5TC8G63XXX-4GB.inc
@@ -0,0 +1,77 @@
+{
+ {
+ {
+ .rank = 0x2,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ },
+ {
+ .rank = 0x2,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ }
+ },
+ {
+ .togcnt1u = 0x29A,
+ .tinit = 0xC8,
+ .trsth = 0x1F4,
+ .togcnt100n = 0x42,
+ .trefi = 0x4E,
+ .tmrd = 0x4,
+ .trfc = 0xEA,
+ .trp = 0xA,
+ .trtw = 0x5,
+ .tal = 0x0,
+ .tcl = 0xA,
+ .tcwl = 0x7,
+ .tras = 0x19,
+ .trc = 0x24,
+ .trcd = 0xA,
+ .trrd = 0x7,
+ .trtp = 0x5,
+ .twr = 0xA,
+ .twtr = 0x5,
+ .texsr = 0x200,
+ .txp = 0x5,
+ .txpdll = 0x10,
+ .tzqcs = 0x40,
+ .tzqcsi = 0x0,
+ .tdqs = 0x1,
+ .tcksre = 0x7,
+ .tcksrx = 0x7,
+ .tcke = 0x4,
+ .tmod = 0xC,
+ .trstl = 0x43,
+ .tzqcl = 0x100,
+ .tmrr = 0x0,
+ .tckesr = 0x5,
+ .tdpd = 0x0
+ },
+ {
+ .dtpr0 = 0x48F9AAB4,
+ .dtpr1 = 0xEA0910,
+ .dtpr2 = 0x1002C200,
+ .mr[0] = 0xA60,
+ .mr[1] = 0x40,
+ .mr[2] = 0x10,
+ .mr[3] = 0x0
+ },
+ .noc_timing = 0x30B25564,
+ .noc_activate = 0x627,
+ .ddrconfig = 3,
+ .ddr_freq = 666*MHz,
+ .dramtype = DDR3,
+ .num_channels = 2,
+ .stride = 13,
+ .odt = 1
+},
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-K4B8G1646Q-4GB.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-K4B8G1646Q-4GB.inc
new file mode 100644
index 0000000000..97a4be479e
--- /dev/null
+++ b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-K4B8G1646Q-4GB.inc
@@ -0,0 +1,77 @@
+{
+ {
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0x10,
+ .cs1_row = 0x10
+ },
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0x10,
+ .cs1_row = 0x10
+ }
+ },
+ {
+ .togcnt1u = 0x29A,
+ .tinit = 0xC8,
+ .trsth = 0x1F4,
+ .togcnt100n = 0x42,
+ .trefi = 0x4E,
+ .tmrd = 0x4,
+ .trfc = 0xEA,
+ .trp = 0xA,
+ .trtw = 0x5,
+ .tal = 0x0,
+ .tcl = 0xA,
+ .tcwl = 0x7,
+ .tras = 0x19,
+ .trc = 0x24,
+ .trcd = 0xA,
+ .trrd = 0x7,
+ .trtp = 0x5,
+ .twr = 0xA,
+ .twtr = 0x5,
+ .texsr = 0x200,
+ .txp = 0x5,
+ .txpdll = 0x10,
+ .tzqcs = 0x40,
+ .tzqcsi = 0x0,
+ .tdqs = 0x1,
+ .tcksre = 0x7,
+ .tcksrx = 0x7,
+ .tcke = 0x4,
+ .tmod = 0xC,
+ .trstl = 0x43,
+ .tzqcl = 0x100,
+ .tmrr = 0x0,
+ .tckesr = 0x5,
+ .tdpd = 0x0
+ },
+ {
+ .dtpr0 = 0x48F9AAB4,
+ .dtpr1 = 0xEA0910,
+ .dtpr2 = 0x1002C200,
+ .mr[0] = 0xA60,
+ .mr[1] = 0x40,
+ .mr[2] = 0x10,
+ .mr[3] = 0x0
+ },
+ .noc_timing = 0x30B25564,
+ .noc_activate = 0x627,
+ .ddrconfig = 4,
+ .ddr_freq = 666*MHz,
+ .dramtype = DDR3,
+ .num_channels = 2,
+ .stride = 13,
+ .odt = 1
+},