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authorDuncan Laurie <dlaurie@chromium.org>2012-06-23 17:02:29 -0700
committerRonald G. Minnich <rminnich@gmail.com>2012-07-25 22:59:43 +0200
commit54cba3b4ad743340de7462e0e5dcec76ee73baed (patch)
tree94e95f2277e66efd0b481847cf329c17810d535c
parent800e950d646d687aa4231e8eced06a0615ba7344 (diff)
SMM: Skip locking SPI registers in finalize step
This is a temporary workaround so the SPI bus can be accessed at runtime in SMM code until the SPI opcode menu is used properly. Change-Id: I93d188c55b66d8dce49fa91a1de53ee195944b30 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1318 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
-rw-r--r--src/southbridge/intel/bd82x6x/finalize.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c
index ed1ebf7a9a..d62600f693 100644
--- a/src/southbridge/intel/bd82x6x/finalize.c
+++ b/src/southbridge/intel/bd82x6x/finalize.c
@@ -31,8 +31,11 @@ void intel_pch_finalize_smm(void)
RCBA32(0x3898) = SPI_OPMENU_LOWER;
RCBA32(0x389c) = SPI_OPMENU_UPPER;
+/* Need to fix SMI driver use of opcode menu */
+#if !CONFIG_ELOG_GSMI
/* Lock SPIBAR */
RCBA32_OR(0x3804, (1 << 15));
+#endif
/* TCLOCKDN: TC Lockdown */
RCBA32_OR(0x0050, (1 << 31));