diff options
| author | Johanna Schander <coreboot@mimoja.de> | 2020-01-06 08:52:49 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-01-10 15:14:02 +0000 |
| commit | 4ddbbd84d971e68a1e51d1518a436f439cf6ef24 (patch) | |
| tree | c9242b92dc14e51f9ae19081a5810b6fb4056491 | |
| parent | fc31158522d9904c9546b410b76bd6c7d739e343 (diff) | |
util/inteltool: Add MCHBAR dumping support for Ice Lake U systems
According to intels datasheet
Document Number: 341078-001
10th Generation Intel® Core™ Processor Families
Volume 2 of 2
we can dump the ICL MCHBAR similiar as on 8th / 9th gen CPUs.
The difference is that on ICL the MCHBAR address is definited by
the bits 38:16 instead of 38:15 giving the constraint that it has
to be 64kbit instead of 32kbit aligned. (Section 3.1.13)
Change-Id: Ia597a4b3738c11cb48ce5808d8459b4a2a768077
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
| -rw-r--r-- | util/inteltool/memory.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index e80f1ba15d..e7523f3501 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -232,6 +232,12 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */ size = 32768; break; + case PCI_DEVICE_ID_INTEL_CORE_10TH_GEN_U: + mchbar_phys = pci_read_long(nb, 0x48); + mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; + mchbar_phys &= 0x0000007fffff0000UL; /* 38:16 */ + size = 32768; + break; default: printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n"); return 1; |