Support for Lanner EM-8510 Board

Signed-off-by: Andreas Schultz <aschultz@tpip.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

---
 src/mainboard/Kconfig                     |    8 ++
 src/mainboard/lanner/Kconfig              |    8 ++
 src/mainboard/lanner/em8510/Kconfig       |   38 +++++++++++
 src/mainboard/lanner/em8510/Makefile.inc  |   21 ++++++
 src/mainboard/lanner/em8510/chip.h        |   23 +++++++
 src/mainboard/lanner/em8510/cmos.layout   |   74 +++++++++++++++++++++
 src/mainboard/lanner/em8510/devicetree.cb |   60 +++++++++++++++++
 src/mainboard/lanner/em8510/irq_tables.c  |   56 ++++++++++++++++
 src/mainboard/lanner/em8510/mainboard.c   |   27 ++++++++
 src/mainboard/lanner/em8510/romstage.c    |  103 +++++++++++++++++++++++++++++
 10 files changed, 418 insertions(+), 0 deletions(-)
 create mode 100644 src/mainboard/lanner/Kconfig
 create mode 100644 src/mainboard/lanner/em8510/Kconfig
 create mode 100644 src/mainboard/lanner/em8510/Makefile.inc
 create mode 100644 src/mainboard/lanner/em8510/chip.h
 create mode 100644 src/mainboard/lanner/em8510/cmos.layout
 create mode 100644 src/mainboard/lanner/em8510/devicetree.cb
 create mode 100644 src/mainboard/lanner/em8510/irq_tables.c
 create mode 100644 src/mainboard/lanner/em8510/mainboard.c
 create mode 100644 src/mainboard/lanner/em8510/romstage.c




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5752 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

10 files changed, 418 insertions, 0 deletions

diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig
index a562db23d7..7f97fc6655 100644
--- a/src/mainboard/Kconfig
+++ b/src/mainboard/Kconfig
@@ -64,6 +64,8 @@ config VENDOR_JETWAY
 	bool "Jetway"
 config VENDOR_KONTRON
 	bool "Kontron"
+config VENDOR_LANNER
+	bool "Lanner"
 config VENDOR_LIPPERT
 	bool "Lippert"
 config VENDOR_MITAC
@@ -270,6 +272,11 @@ config MAINBOARD_VENDOR
 
 config MAINBOARD_VENDOR
 	string
+	default "Lanner"
+	depends on VENDOR_LANNER
+
+config MAINBOARD_VENDOR
+	string
 	default "Lippert"
 	depends on VENDOR_LIPPERT
 
@@ -443,6 +450,7 @@ source "src/mainboard/intel/Kconfig"
 source "src/mainboard/iwill/Kconfig"
 source "src/mainboard/jetway/Kconfig"
 source "src/mainboard/kontron/Kconfig"
+source "src/mainboard/lanner/Kconfig"
 source "src/mainboard/lippert/Kconfig"
 source "src/mainboard/mitac/Kconfig"
 source "src/mainboard/msi/Kconfig"
diff --git a/src/mainboard/lanner/Kconfig b/src/mainboard/lanner/Kconfig
new file mode 100644
index 0000000000..f499efa6d7
--- /dev/null
+++ b/src/mainboard/lanner/Kconfig
@@ -0,0 +1,8 @@
+choice
+	prompt "Mainboard model"
+	depends on VENDOR_LANNER
+
+source "src/mainboard/lanner/em8510/Kconfig"
+
+endchoice
+
diff --git a/src/mainboard/lanner/em8510/Kconfig b/src/mainboard/lanner/em8510/Kconfig
new file mode 100644
index 0000000000..97d294922d
--- /dev/null
+++ b/src/mainboard/lanner/em8510/Kconfig
@@ -0,0 +1,38 @@
+config BOARD_LANNER_EM8510
+	bool "EM-8510"
+	select ARCH_X86
+	select CPU_INTEL_SOCKET_MPGA479M
+	select NORTHBRIDGE_INTEL_I855
+	select SOUTHBRIDGE_INTEL_I82801DX
+	select SUPERIO_WINBOND_W83627THF
+	select HAVE_OPTION_TABLE
+	select HAVE_PIRQ_TABLE
+	select HAVE_HARD_RESET
+	select BOARD_ROMSIZE_KB_512
+	select USE_DCACHE_RAM
+	select TINY_BOOTBLOCK
+
+config MAINBOARD_DIR
+	string
+	default lanner/em8510
+	depends on BOARD_LANNER_EM8510
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "EM-8510"
+	depends on BOARD_LANNER_EM8510
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xffdf8000
+	depends on BOARD_LANNER_EM8510
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x8000
+	depends on BOARD_LANNER_EM8510
+
+config IRQ_SLOT_COUNT
+	int
+	default 10
+	depends on BOARD_LANNER_EM8510
diff --git a/src/mainboard/lanner/em8510/Makefile.inc b/src/mainboard/lanner/em8510/Makefile.inc
new file mode 100644
index 0000000000..6b93f647b0
--- /dev/null
+++ b/src/mainboard/lanner/em8510/Makefile.inc
@@ -0,0 +1,21 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Travelping GmbH <info@travelping.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+ROMCCFLAGS := -mcpu=p3 -O
diff --git a/src/mainboard/lanner/em8510/chip.h b/src/mainboard/lanner/em8510/chip.h
new file mode 100644
index 0000000000..96d8705b38
--- /dev/null
+++ b/src/mainboard/lanner/em8510/chip.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Travelping GmbH <info@travelping.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {};
diff --git a/src/mainboard/lanner/em8510/cmos.layout b/src/mainboard/lanner/em8510/cmos.layout
new file mode 100644
index 0000000000..c1354a2866
--- /dev/null
+++ b/src/mainboard/lanner/em8510/cmos.layout
@@ -0,0 +1,74 @@
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432          8       h       0        boot_countdown
+1008         16      h       0        check_sum
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+
+checksums
+
+checksum 392 1007 1008
+
+
diff --git a/src/mainboard/lanner/em8510/devicetree.cb b/src/mainboard/lanner/em8510/devicetree.cb
new file mode 100644
index 0000000000..7df1443066
--- /dev/null
+++ b/src/mainboard/lanner/em8510/devicetree.cb
@@ -0,0 +1,60 @@
+chip northbridge/intel/i855
+	device pci_domain 0 on
+		device pci 0.0 on end
+		chip southbridge/intel/i82801dx
+#			pci 11.0 on end
+#			pci 11.1 on end
+#			pci 11.2 on end
+#			pci 11.3 on end
+#			pci 11.4 on end
+#			pci 11.5 on end
+#			pci 11.6 on end
+#			pci 12.0 on end
+			register "enable_usb" = "0"
+			register "enable_native_ide" = "0"
+			device pci 1f.0 on
+				chip superio/winbond/w83627thf # link 1
+                		        device pnp 2e.0 on      #  Floppy
+                	        	        io 0x60 = 0x3f0
+                	                	irq 0x70 = 6
+                	                	drq 0x74 = 2
+					end
+                	       		device pnp 2e.1 on      #  Parallel Port
+                	                       io 0x60 = 0x378
+                	                       irq 0x70 = 7
+					       end
+                	        	device pnp 2e.2 on      #  Com1
+                	        	       io 0x60 = 0x3f8
+                	            	       irq 0x70 = 4
+					end
+                	      		device pnp 2e.3 on      #  Com2
+                	                       io 0x60 = 0x2f8
+                	                       irq 0x70 = 3
+					end
+                	 	        device pnp 2e.5 on      #  Keyboard
+                	 	                io 0x60 = 0x60
+                		                io 0x62 = 0x64
+                		                irq 0x70 = 1
+						irq 0x72 = 12
+					end
+                		        device pnp 2e.6 off end #  CIR
+                		        device pnp 2e.7 off end #  GAME_MIDI_GIPO1
+                	 	        device pnp 2e.8 off end #  GPIO2
+                	 	        device pnp 2e.9 off end #  GPIO3
+                	 	        device pnp 2e.a off end #  ACPI
+                	 	        device pnp 2e.b on      #  HW Monitor
+ 						 io 0x60 = 0x290
+					end
+					register "com1" = "{1}"
+				#	register "com1" = "{1, 0, 0x3f8, 4}"
+				#	register "lpt" = "{1}"
+				end
+                	end
+		end
+	end
+	device lapic_cluster 0 on
+		chip cpu/intel/socket_mPGA479M
+			device lapic 0 on end
+		end
+	end
+end
diff --git a/src/mainboard/lanner/em8510/irq_tables.c b/src/mainboard/lanner/em8510/irq_tables.c
new file mode 100644
index 0000000000..5b42952d32
--- /dev/null
+++ b/src/mainboard/lanner/em8510/irq_tables.c
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Travelping GmbH <info@travelping.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,		/* u32 signature */
+	PIRQ_VERSION,		/* u16 version */
+	32 + 16 * 10,		/* Max. number of devices on the bus */
+	0x00,			/* Interrupt router bus */
+	(0x1f << 3) | 0x0,	/* Interrupt router dev */
+	0x1e20,			/* IRQs devoted exclusively to PCI usage */
+	0x8086,			/* Vendor */
+	0x24cc,			/* Device */
+	0,			/* Miniport */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0x39,			/* Checksum (has to be set to some value that
+				 * would give 0 after the sum of all bytes
+				 * for this structure (including checksum).
+                                 */
+	{
+		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+		{0x01, (0x0f << 3) | 0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x1, 0x0},
+		{0x01, (0x0a << 3) | 0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x2, 0x0},
+		{0x01, (0x05 << 3) | 0x0, {{0x68, 0xdeb8}, {0x69, 0xdeb8}, {0x6a, 0xdeb8}, {0x6b, 0xdeb8}}, 0x3, 0x0},
+		{0x01, (0x06 << 3) | 0x0, {{0x69, 0xdeb8}, {0x6a, 0xdeb8}, {0x6b, 0xdeb8}, {0x68, 0xdeb8}}, 0x4, 0x0},
+		{0x01, (0x07 << 3) | 0x0, {{0x6a, 0xdeb8}, {0x6b, 0xdeb8}, {0x68, 0xdeb8}, {0x69, 0xdeb8}}, 0x5, 0x0},
+		{0x01, (0x09 << 3) | 0x0, {{0x6b, 0xdeb8}, {0x68, 0xdeb8}, {0x69, 0xdeb8}, {0x6a, 0xdeb8}}, 0x6, 0x0},
+		{0x00, (0x1e << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x0, 0x0},
+		{0x00, (0x02 << 3) | 0x0, {{0x60, 0xdeb8}, {0x60, 0xdeb8}, {0x60, 0xdeb8}, {0x60, 0xdeb8}}, 0x0, 0x0},
+		{0x00, (0x1f << 3) | 0x0, {{0x62, 0xdeb8}, {0x61, 0xdeb8}, {0x60, 0xdeb8}, {0x63, 0xdeb8}}, 0x0, 0x0},
+		{0x00, (0x1d << 3) | 0x0, {{0x60, 0xdeb8}, {0x63, 0xdeb8}, {0x62, 0xdeb8}, {0x6b, 0xdeb8}}, 0x0, 0x0},
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr);
+}
diff --git a/src/mainboard/lanner/em8510/mainboard.c b/src/mainboard/lanner/em8510/mainboard.c
new file mode 100644
index 0000000000..4a20d2559d
--- /dev/null
+++ b/src/mainboard/lanner/em8510/mainboard.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Travelping GmbH <info@travelping.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME("LANNER EM-8510 Mainboard")
+};
+
diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c
new file mode 100644
index 0000000000..9a33fa8812
--- /dev/null
+++ b/src/mainboard/lanner/em8510/romstage.c
@@ -0,0 +1,103 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Original take from digitallogic/adl855pc
+ *
+ * Copyright (C) 2010 Travelping GmbH <info@travelping.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#include <stdlib.h>
+#include "pc80/udelay_io.c"
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include "lib/ramtest.c"
+#include "southbridge/intel/i82801dx/i82801dx.h"
+#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
+#include "northbridge/intel/i855/raminit.h"
+#include "northbridge/intel/i855/debug.c"
+#include "superio/winbond/w83627thf/w83627thf_early_serial.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627THF_SP1)
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+	return smbus_read_byte(device, address);
+}
+
+#include "northbridge/intel/i855/raminit.c"
+#include "northbridge/intel/i855/reset_test.c"
+#include "lib/generic_sdram.c"
+
+void main(unsigned long bist)
+{
+	static const struct mem_controller memctrl[] = {
+		{
+			.d0 = PCI_DEV(0, 0, 1),
+			.channel0 = { (0xa<<3)|0, 0 },
+		},
+	};
+
+	if (bist == 0) {
+#if 0
+		enable_lapic();
+		init_timer();
+#endif
+	}
+
+        w83627thf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+        uart_init();
+        console_init();
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+#if 0
+	print_pci_devices();
+#endif
+
+	if(!bios_reset_detected()) {
+        	enable_smbus();
+#if 1
+		dump_spd_registers(&memctrl[0]);
+		dump_smbus_registers();
+#endif
+
+		sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
+
+	}
+
+#if 0
+	dump_pci_devices();
+	dump_pci_device(PCI_DEV(0, 0, 0));
+
+	// Check all of memory
+	ram_check(0x00000000, msr.lo+(msr.hi<<32));
+	// Check 16MB of memory @ 0
+	ram_check(0x00000000, 0x01000000);
+	// Check 16MB of memory @ 2GB
+	ram_check(0x80000000, 0x81000000);
+#endif
+}
+