diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2016-09-02 16:10:58 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-09-04 20:17:55 +0200 |
| commit | 4551bf6dbfa28d63d657542be372bf5fb15ee5f9 (patch) | |
| tree | 46ba150336af185e542868dbd99e76eaaa6f4370 | |
| parent | 297c5595629ddfebc15efce92b8a3b0201a1c839 (diff) | |
intel/minnowmax: Enable all PCIe ports
A recently announced Turbot system populates two Ethernet
controllers. Enable the remaining disabled PCIe port.
Also add a clarifying comment regarding the port associated
with Function 0. Coreboot must not be allowed to disable the
function which breaks PCI compatibility.
Change-Id: I2815ba7e6d68b9898091fbc21c96eeeb49c8e05a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/16429
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
| -rw-r--r-- | src/mainboard/intel/minnowmax/devicetree.cb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb index fb26fdf995..873b5898e7 100644 --- a/src/mainboard/intel/minnowmax/devicetree.cb +++ b/src/mainboard/intel/minnowmax/devicetree.cb @@ -76,8 +76,8 @@ chip soc/intel/fsp_baytrail device pci 18.7 on end # 8086 0F47 - I2C Port 7 (6) HSEC device pci 1a.0 on end # 8086 0F18 - TXE - device pci 1b.0 off end # 8086 0F04 - HD Audio - - device pci 1c.0 on end # 8086 0F48 - PCIe Port 1 (0) - - device pci 1c.1 off end # 8086 0F4A - PCIe Port 2 (1) - + device pci 1c.0 on end # 8086 0F48 - PCIe Port 1 (0) Must remain on + device pci 1c.1 on end # 8086 0F4A - PCIe Port 2 (1) Onboard GBE (some models) device pci 1c.2 on end # 8086 0F4C - PCIe Port 3 (2) Onboard GBE device pci 1c.3 on end # 8086 0F4E - PCIe Port 4 (3) HSEC device pci 1d.0 on end # 8086 0F34 - USB EHCI - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime |