mainboard/facebook/fbg1701: Do initial mainboard commit

Initial support for Facebook FBG-1701 system.
coreboot implementation based on Intel Strago mainboard.

Configure 'Onboard memory manufacturer' which must match HW.

BUG=N/A
TEST=booting SeaBIOS and Linux 4.15+ kernel on Facebook FBG-1701

Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

29 files changed, 2038 insertions, 0 deletions

diff --git a/Documentation/mainboard/facebook/fbg1701.md b/Documentation/mainboard/facebook/fbg1701.md
new file mode 100644
index 0000000000..89e8a6abbc
--- /dev/null
+++ b/Documentation/mainboard/facebook/fbg1701.md
@@ -0,0 +1,83 @@
+# Facebook FBG-1701
+
+This page describes how to run coreboot on the Facebook FBG1701.
+
+FBG1701 are assembled with different onboard memory modules:
+	Rev 1.0	Onboard Samsung K4B8G1646D-MYKO memory
+	Rev 1.1 and 1.2	Onboard Micron MT41K512M16HA-125A memory
+
+Use make menuconfig to configure `onboard memory manufacturer` in Mainboard
+menu.
+
+## Required blobs
+
+This board currently requires:
+fsp blob	3rdparty/fsp/BraswellFspBinPkg/FspBin/BSWFSP.fd
+Microcode	Intel Braswell cpuid 1046C4 version 410
+		(Used pre-build binary retrieved from Intel site)
+
+## Flashing coreboot
+
+### Internal programming
+
+The main SPI flash can be accessed using [flashrom].
+
+### External programming
+
+The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip.
+This chip is located to the top middle side of the board. It's located
+between SoC and Q7 connector. Use clip (or solder wires) to program
+the chip.
+Specifically, it's a Winbond W25Q64FW (1.8V), whose datasheet can be found
+[here][W25Q64FW].
+
+The system has an external flash chip which is a 8 MiB soldered SOIC-8 chip.
+This chip is located in the middle of carrier board close to the flex cable
+connection.
+Specifically, it's a Winbond W25Q64FV (3.3V), whose datasheet can be found
+[here][W25Q64FV].
+
+## Known issues
+
+- None
+
+## Untested
+
+- hardware monitor
+- SDIO
+- Full Embedded Controller support
+
+## Working
+
+- USB
+- Gigabit Ethernet
+- integrated graphics
+- flashrom
+- external graphics
+- PCIe
+- eMMC
+- SATA
+- serial port
+- SMBus
+- HDA
+- initialization with FSP MR2
+- SeaBIOS payload
+- Embedded Linux (Ubuntu 4.15+)
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| SoC              | Intel Atom Processor N3710                       |
++------------------+--------------------------------------------------+
+| CPU              | Intel Braswell (N3710)                           |
++------------------+--------------------------------------------------+
+| Super I/O, EC    | ITE8256                                          |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel Management Engine                          |
++------------------+--------------------------------------------------+
+```
+
+[W25Q64FW]: https://www.winbond.com/resource-files/w25q64fw%20revn%2005182017%20sfdp.pdf
+[W25Q64FV]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
+[flashrom]: https://flashrom.org/Flashrom
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index fb4f5022aa..f63ef763fb 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -30,6 +30,10 @@ The boards in this section are not real mainboards, but emulators.
 - [IceLake RVP](intel/icelake_rvp.md)
 - [KBLRVP11](intel/kblrvp11.md)
 
+## Facebook
+
+- [FBG-1701](facebook/fbg1701.md)
+
 ## Foxconn
 
 - [D41S](foxconn/d41s.md)
diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig
new file mode 100644
index 0000000000..3f451945b4
--- /dev/null
+++ b/src/mainboard/facebook/fbg1701/Kconfig
@@ -0,0 +1,105 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018-2019 Eltan B.V.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+if BOARD_FACEBOOK_FBG1701
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_8192
+	select HAVE_ACPI_TABLES
+	select HAVE_OPTION_TABLE
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM2
+	select SOC_INTEL_BRASWELL
+	select PCIEXP_L1_SUB_STATE
+	select HAVE_FSP_BIN
+	select CACHE_MRC_SETTINGS
+	select DISABLE_HPET
+	select GENERIC_SPD_BIN
+
+choice
+	prompt "Onboard memory manufacturer"
+	default ONBOARD_MICRON_MEM
+
+config ONBOARD_SAMSUNG_MEM
+	bool "Samsung"
+	help
+	  Samsung K4B8G1646D memory
+
+config ONBOARD_MICRON_MEM
+	bool "Micron"
+	help
+	  Micron MT41K512M16HA memory
+endchoice
+
+config MAINBOARD_DIR
+	string
+	default facebook/fbg1701
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "FBG-1701"
+
+config CBFS_SIZE
+	hex
+	default 0x00800000
+
+config CPU_MICROCODE_CBFS_LEN
+	hex
+	default 0x10C00
+	help
+	  This should be updated when the microcode patch changes.
+
+config CPU_MICROCODE_CBFS_LOC
+	hex
+	default 0xFFFE9400
+
+config MRC_SETTINGS_CACHE_SIZE
+	hex
+	default 0x08000
+
+config FSP_LOC
+	hex
+	default 0xfff9c000
+
+config FSP1_1_DISPLAY_LOGO
+	bool
+	default n
+
+config BOOTBLOCK_LOC
+	hex
+	default 0xFFFF0000
+
+config BOOTBLOCK_SIZE
+	hex
+	default 0x10000
+
+config SPI_FLASH_INCLUDE_ALL_DRIVERS
+	bool
+	default n
+
+config SPI_FLASH_WINBOND
+	bool
+	default y
+
+config TPM_INIT
+	bool "TPM Setup in RAMSTAGE"
+	default n
+
+config C_ENV_BOOTBLOCK_SIZE
+	hex "C Bootblock Size"
+	default 0x4000
+
+endif # BOARD_FACEBOOK_FBG1701
diff --git a/src/mainboard/facebook/fbg1701/Kconfig.name b/src/mainboard/facebook/fbg1701/Kconfig.name
new file mode 100644
index 0000000000..1ead7d587f
--- /dev/null
+++ b/src/mainboard/facebook/fbg1701/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_FACEBOOK_FBG1701
+	bool "fbg1701"
diff --git a/src/mainboard/facebook/fbg1701/Makefile.inc b/src/mainboard/facebook/fbg1701/Makefile.inc
new file mode 100644
index 0000000000..07309c564c
--- /dev/null
+++ b/src/mainboard/facebook/fbg1701/Makefile.inc
@@ -0,0 +1,34 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+## Copyright (C) 2015 Intel Corp.
+## Copyright (C) 2018-2019 Eltan B.V.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += com_init.c
+
+ramstage-y += gpio.c
+ramstage-y += hda_verb.c
+ramstage-y += irqroute.c
+ramstage-$(CONFIG_FSP1_1_DISPLAY_LOGO) += logo.c
+ramstage-y += ramstage.c
+ramstage-y += w25q64.c
+
+cbfs-files-$(CONFIG_FSP1_1_DISPLAY_LOGO) += logo.bmp
+logo.bmp-file := $(call strip_quotes,$(CONFIG_FSP1_1_LOGO_FILE_NAME))
+logo.bmp-type := raw
+logo.bmp-compression := LZMA
+
+# Order of names in SPD_SOURCES is important!
+SPD_SOURCES  = SAMSUNG_K4B8G1646D-MYKO
+SPD_SOURCES += MICRON_MT41K512M16HA-125A
diff --git a/src/mainboard/facebook/fbg1701/acpi/ec.asl b/src/mainboard/facebook/fbg1701/acpi/ec.asl
new file mode 100644
index 0000000000..3c9d818bae
--- /dev/null
+++ b/src/mainboard/facebook/fbg1701/acpi/ec.asl
@@ -0,0 +1,14 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
diff --git a/src/mainboard/facebook/fbg1701/acpi/mainboard.asl b/src/mainboard/facebook/fbg1701/acpi/mainboard.asl
new file mode 100644
index 0000000000..9575748446
--- /dev/null
+++ b/src/mainboard/facebook/fbg1701/acpi/mainboard.asl
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2018 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "onboard.h"
+
+Scope (\_SB)
+{
+	Device (PWRB)
+	{
+		Name (_HID, EisaId ("PNP0C0C"))
+		Name (_UID, 1)
+	}
+}
+
+/*
+ * Onboard CPLD
+ */
+Scope (\_SB.PCI0.LPCB)
+{
+	Device (CPLD)		/* Onboard CPLD */
+	{
+		Name(_HID, EISAID("PNP0C01"))
+		Name(_CRS, ResourceTemplate()
+		{
+			/* Reserve 0x280 to 0x2BF for the CPLD */
+			FixedIO (0x0280, 0x40)
+			IRQNoFlags () {7}
+		})
+	}
+}
diff --git a/src/mainboard/facebook/fbg1701/acpi/sleepstates.asl b/src/mainboard/facebook/fbg1701/acpi/sleepstates.asl
new file mode 100644
index 0000000000..428fda2a01
--- /dev/null
+++ b/src/mainboard/facebook/fbg1701/acpi/sleepstates.asl
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2018 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Name(\_S0, Package(){0x0,0x0,0x0,0x0})
+Name(\_S4, Package(){0x6,0x6,0x0,0x0})
+Name(\_S5, Package(){0x7,0x7,0x0,0x0})
diff --git a/src/mainboard/facebook/fbg1701/acpi/superio.asl b/src/mainboard/facebook/fbg1701/acpi/superio.asl
new file mode 100644
index 0000000000..468c95c531
--- /dev/null
+++ b/src/mainboard/facebook/fbg1701/acpi/superio.asl
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2018-2019 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* mainboard configuration */
+#include "onboard.h"
+
+Device (COM1) {
+	Name (_HID, EISAID ("PNP0501"))
+	Name (_UID, 1)
+	Name (_ADR, 0)
+
+	Method (_STA, 0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+
+	Name (_CRS, ResourceTemplate ()
+	{
+		FixedIO (0x03F8, 0x08)
+		FixedIO (0x6E, 0x02)
+		IRQNoFlags () {4}
+	})
+
+	Name (_PRS, ResourceTemplate ()
+	{
+		StartDependentFn (0, 0) {
+			FixedIO (0x03F8, 0x08)
+			FixedIO (0x6E, 0x02)
+			IRQNoFlags () {4}
+		}
+		EndDependentFn ()
+	})
+}
diff --git a/src/mainboard/facebook/fbg1701/acpi_tables.c b/src/mainboard/facebook/fbg1701/acpi_tables.c
new file mode 100644
index 0000000000..15c955afc2
--- /dev/null
+++ b/src/mainboard/facebook/fbg1701/acpi_tables.c
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2018 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	acpi_init_gnvs(gnvs);
+
+	/* Enable USB ports in S3 */
+	gnvs->s3u0 = 1;
+	gnvs->s3u1 = 1;
+
+	/* Disable USB ports in S5 */
+	gnvs->s5u0 = 0;
+	gnvs->s5u1 = 0;
+
+	/* Disable DPTF */
+	gnvs->dpte = 0;
+
+	/* PMIC is configured in I2C1, hide it for the OS */
+	gnvs->dev.lpss_en[LPSS_NVS_I2C2] = 0;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* Local APICs */
+	current = acpi_create_madt_lapics(current);
+
+	/* IOAPIC */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				2, IO_APIC_ADDR, 0);
+
+	current = acpi_madt_irq_overrides(current);
+
+	return current;
+}
diff --git a/src/mainboard/facebook/fbg1701/board_info.txt b/src/mainboard/facebook/fbg1701/board_info.txt
new file mode 100644
index 0000000000..41d91fd2be
--- /dev/null
+++ b/src/mainboard/facebook/fbg1701/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Facebook
+Board name: FBG-1701
+Category: sbc
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/facebook/fbg1701/cmos.layout b/src/mainboard/facebook/fbg1701/cmos.layout
new file mode 100644
index 0000000000..c293c5f989
--- /dev/null
+++ b/src/mainboard/facebook/fbg1701/cmos.layout
@@ -0,0 +1,121 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2015 Intel Corp.
+## Copyright (C) 2018 Eltan B.V.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+# -----------------------------------------------------------------
+# Status Register A
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96           4       r       0        status_c_rsvd
+#100          1       r       0        uf_flag
+#101          1       r       0        af_flag
+#102          1       r       0        pf_flag
+#103          1       r       0        irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104          7       r       0        status_d_rsvd
+#111          1       r       0        valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112          8       r       0        diag_rsvd1
+
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+# reboot_counter reserved for core, not used by platform.
+384          1       e       4        boot_option
+388          4       h       0        reboot_counter
+#390          2       r       0        unused
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+#392          3       r       0        unused
+395          4       e       6        debug_level
+#399          1       r       0        unused
+
+# coreboot config options: cpu
+#400          1       e       2        unused
+#401          7       r       0        unused
+
+# coreboot config options: southbridge
+408          1       e       1        nmi
+409          2       e       7        power_on_after_fail
+#411          5       r       0        unused
+
+# coreboot config options: bootloader
+#416        568       r        0       unused
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+#1000        24       r       0        amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+6     0     Emergency
+6     1     Alert
+6     2     Critical
+6     3     Error
+6     4     Warning
+6     5     Notice
+6     6     Info
+6     7     Debug
+6     8     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/facebook/fbg1701/com_init.c b/src/mainboard/facebook/fbg1701/com_init.c
new file mode 100644
index 0000000000..f19aba311c
--- /dev/null
+++ b/src/mainboard/facebook/fbg1701/com_init.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2018-2019 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <device/pnp_ops.h>
+#include "onboard.h"
+
+#define SERIAL_DEV PNP_DEV(ITE8528_CMD_PORT, 1) /* ITE8528 UART1 */
+
+void bootblock_mainboard_early_init(void)
+{
+	/* Enable the serial port inside the EC */
+	pnp_set_logical_device(SERIAL_DEV);
+	pnp_set_enable(SERIAL_DEV, 1);
+}
diff --git a/src/mainboard/facebook/fbg1701/devicetree.cb b/src/mainboard/facebook/fbg1701/devicetree.cb
new file mode 100644
index 0000000000..3c82a034b4
--- /dev/null
+++ b/src/mainboard/facebook/fbg1701/devicetree.cb
@@ -0,0 +1,131 @@
+chip soc/intel/braswell
+
+	############################################################
+	# Set the parameters for MemoryInit
+	############################################################
+
+	register "PcdMrcInitTsegSize" = "8"	# SMM Region size in MiB
+
+	register "PcdMrcInitMmioSize" = "0x0800"
+	register "PcdMrcInitSpdAddr1" = "0xa0"
+	register "PcdMrcInitSpdAddr2" = "0xa2"
+	register "PcdIgdDvmt50PreAlloc" = "1"
+	register "PcdApertureSize" = "2"
+	register "PcdGttSize" = "1"
+	register "PcdDvfsEnable" = "0"
+	register "PcdCaMirrorEn" = "1"
+
+	############################################################
+	# Set the parameters for SiliconInit
+	############################################################
+
+	register "PcdSdcardMode" = "PCH_DISABLED"
+	register "PcdEnableHsuart0" = "0"
+	register "PcdEnableHsuart1" = "0"
+	register "PcdEnableAzalia" = "1"
+	register "PcdEnableXhci" = "1"
+	register "PcdEnableLpe" = "0"
+	register "PcdEnableDma0" = "0"
+	register "PcdEnableDma1" = "0"
+	register "PcdEnableI2C0" = "0"
+	register "PcdEnableI2C1" = "0"
+	register "PcdEnableI2C2" = "0"
+	register "PcdEnableI2C3" = "0"
+	register "PcdEnableI2C4" = "0"
+	register "PcdEnableI2C5" = "0"
+	register "PcdEnableI2C6" = "0"
+	register "PunitPwrConfigDisable" = "0"	# Enable SVID
+	register "ChvSvidConfig" = "1"
+	register "PcdEmmcMode" = "PCH_PCI_MODE"
+	register "PcdUsb3ClkSsc" = "1"
+	register "PcdDispClkSsc" = "1"
+	register "PcdSataClkSsc" = "1"
+	register "PcdEnableSata" = "0"		# Disable SATA
+	register "Usb2Port0PerPortPeTxiSet" = "7"
+	register "Usb2Port0PerPortTxiSet" = "5"
+	register "Usb2Port0IUsbTxEmphasisEn" = "2"
+	register "Usb2Port0PerPortTxPeHalf" = "1"
+	register "Usb2Port1PerPortPeTxiSet" = "7"
+	register "Usb2Port1PerPortTxiSet" = "3"
+	register "Usb2Port1IUsbTxEmphasisEn" = "2"
+	register "Usb2Port1PerPortTxPeHalf" = "1"
+	register "Usb2Port2PerPortPeTxiSet" = "7"
+	register "Usb2Port2PerPortTxiSet" = "3"
+	register "Usb2Port2IUsbTxEmphasisEn" = "2"
+	register "Usb2Port2PerPortTxPeHalf" = "1"
+	register "Usb2Port3PerPortPeTxiSet" = "7"
+	register "Usb2Port3PerPortTxiSet" = "3"
+	register "Usb2Port3IUsbTxEmphasisEn" = "2"
+	register "Usb2Port3PerPortTxPeHalf" = "1"
+	register "Usb2Port4PerPortPeTxiSet" = "7"
+	register "Usb2Port4PerPortTxiSet" = "3"
+	register "Usb2Port4IUsbTxEmphasisEn" = "2"
+	register "Usb2Port4PerPortTxPeHalf" = "1"
+	register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a"
+	register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
+	register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
+	register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
+	register "PcdSataInterfaceSpeed" = "3"
+	register "PcdPchSsicEnable" = "1"
+	register "PcdRtcLock" = "0"	# Disable RTC access locking to NVRAM
+	register "PMIC_I2CBus" = "0"
+	register "ISPEnable" = "0"	# Disable IUNIT
+	register "ISPPciDevConfig" = "3"
+	register "PcdSdDetectChk" = "0" # Disable SD card detect
+	register "DptfDisable" = "1"
+
+	# LPE audio codec settings
+	register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
+
+	# Enable devices in PCI mode
+	register "lpss_acpi_mode" = "0"
+	register "emmc_acpi_mode" = "0"
+	register "sd_acpi_mode" = "0"
+	register "lpe_acpi_mode" = "0"
+
+	# Disable SLP_X stretching after SUS power well fail.
+	register "disable_slp_x_stretch_sus_fail" = "1"
+
+	# Allow PCIe devices to wake system from suspend
+	register "pcie_wake_enable" = "1"
+
+	# CPLD requires continuous mode
+	register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		device pci 00.0 on end	# 8086 2280 - SoC router
+		device pci 02.0 on end	# 8086 22B1 - GFX
+		device pci 0b.0 off end	# 8086 22DC - PUNIT/DPTF
+		device pci 10.0 on end	# 8086 2294 - MMC Port
+		device pci 12.0 on end	# 8086 0F16 - SD Port
+		device pci 13.0 off end	# 8086 22a3 - SATA Port
+		device pci 14.0 on end	# 8086 22b5 - USB XHCI - Only 1 USB controller at a time
+		device pci 18.0 off end	# 8086 22c0 - SIO - DMA
+		device pci 18.1 off end	# 8086 22c1 -   I2C Port 1
+		device pci 18.2 off end	# 8086 22c2 -   I2C Port 2
+		device pci 18.3 off end	# 8086 22c3 -   I2C Port 3
+		device pci 18.4 off end	# 8086 22c4 -   I2C Port 4
+		device pci 18.5 off end	# 8086 22c5 -   I2C Port 5
+		device pci 18.6 off end	# 8086 22c6 -   I2C Port 6
+		device pci 18.7 off end	# 8086 22c7 -   I2C Port 7
+		device pci 1a.0 on end	# 8086 2298 - Trusted Execution Engine
+		device pci 1b.0 on end	# 8086 2284 - HD Audio
+		device pci 1c.0 on end	# 8086 0000 - PCIe Root Port 1
+		device pci 1c.1 off end	# 8086 0000 - PCIe Root Port 2
+		device pci 1c.2 off end	# 8086 0000 - PCIe Root Port 3
+		device pci 1c.3 on end	# 8086 0000 - PCIe Root Port 4
+		device pci 1e.0 off end	# 8086 2286 - SIO - DMA
+		device pci 1e.3 off end	# 8086 228a -   HSUART 1
+		device pci 1e.4 off end	# 8086 228c -   HSUART 2
+		device pci 1f.0 on	# 8086 229c - LPC bridge
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end # LPC Bridge
+		device pci 1f.3 on end	# 8086 2292 - SMBus 0
+	end
+end
diff --git a/src/mainboard/facebook/fbg1701/dsdt.asl b/src/mainboard/facebook/fbg1701/dsdt.asl
new file mode 100644
index 0000000000..4eea7b93f4
--- /dev/null
+++ b/src/mainboard/facebook/fbg1701/dsdt.asl
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2015-2018 Intel Corp.
+ * Copyright (C) 2018 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		/* DSDT revision: ACPI v2.0 and up */
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	/* OEM revision */
+)
+{
+	/* Some generic macros */
+	#include <acpi/platform.asl>
+
+	/* global NVS and variables */
+	#include <acpi/globalnvs.asl>
+
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <acpi/southcluster.asl>
+		}
+	}
+
+	/* Chipset specific sleep states */
+	#include "acpi/sleepstates.asl"
+	#include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/facebook/fbg1701/fadt.c b/src/mainboard/facebook/fbg1701/fadt.c
new file mode 100644
index 0000000000..73adfad94c
--- /dev/null
+++ b/src/mainboard/facebook/fbg1701/fadt.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2018-2019 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/acpi.h>
+
+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+
+	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = sizeof(acpi_fadt_t);
+	header->revision = 3;
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+	header->asl_compiler_revision = 1;
+
+	fadt->firmware_ctrl = (unsigned long) facs;
+	fadt->dsdt = (unsigned long) dsdt;
+	fadt->preferred_pm_profile = PM_MOBILE;
+
+	fadt->x_firmware_ctl_l = (unsigned long)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (unsigned long)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	acpi_fill_in_fadt(fadt);
+
+	fadt->iapc_boot_arch &= ~ACPI_FADT_8042;
+
+	header->checksum =
+	    acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/facebook/fbg1701/gpio.c b/src/mainboard/facebook/fbg1701/gpio.c
new file mode 100644
index 0000000000..5a73ca9148
--- /dev/null
+++ b/src/mainboard/facebook/fbg1701/gpio.c
@@ -0,0 +1,253 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2018 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/gpio.h>
+
+/* South East Community */
+static const struct soc_gpio_map gpse_gpio_map[] = {
+	Native_M1,/* 00 MF_PLT_CLK0 */
+	GPIO_NC, /* 01 PWM1 */
+	GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */
+	GPIO_NC, /* 03 MF_PLT_CLK4 */
+	GPIO_NC, /* 04 MF_PLT_CLK3 */
+	GPIO_NC, /* PWM0 05 */
+	GPIO_NC, /* 06 MF_PLT_CLK5 */
+	GPIO_NC, /* 07 MF_PLT_CLK2 */
+	GPIO_NC, /* 15 SDMMC2_D3_CD_B */
+	Native_M1, /* 16 SDMMC1_CLK */
+	NATIVE_PU20K(1), /* 17 SDMMC1_D0 */
+	GPIO_NC, /* 18 SDMMC2_D1 */
+	GPIO_NC, /* 19 SDMMC2_CLK */
+	NATIVE_PU20K(1),/* 20 SDMMC1_D2 */
+	GPIO_NC, /* 21 SDMMC2_D2 */
+	GPIO_NC, /* 22 SDMMC2_CMD  */
+	NATIVE_PU20K(1), /* 23 SDMMC1_CMD */
+	NATIVE_PU20K(1), /* 24 SDMMC1_D1 */
+	GPIO_NC, /* 25 SDMMC2_D0 */
+	NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */
+	NATIVE_PU20K(1), /* 30 SDMMC3_D1 */
+	Native_M1, /* 31 SDMMC3_CLK */
+	NATIVE_PU20K(1), /* 32 SDMMC3_D3 */
+	NATIVE_PU20K(1), /* 33 SDMMC3_D2 */
+	NATIVE_PU20K(1), /* 34 SDMMC3_CMD */
+	NATIVE_PU20K(1), /* 35 SDMMC3_D0 */
+	NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */
+	NATIVE_PU20K(1), /* 46 LPC_CLKRUNB */
+	NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */
+	Native_M1, /* 48 LPC_FRAMEB */
+	Native_M1, /* 49 MF_LPC_CLKOUT1 */
+	NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */
+	Native_M1, /* 51 MF_LPC_CLKOUT0 */
+	NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */
+	Native_M1,/* SPI1_MISO */
+	Native_M1, /* 61 SPI1_CS0_B */
+	Native_M1, /* SPI1_CLK */
+	NATIVE_PU20K(1), /* 63 MMC1_D6 */
+	Native_M1, /* 62 SPI1_MOSI */
+	NATIVE_PU20K(1), /* 65 MMC1_D5 */
+	GPIO_NC, /* 66 SPI1_CS1_B */
+	NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */
+	NATIVE_PU20K(1), /* 68 MMC1_D7 */
+	GPIO_NC, /* 69 MMC1_RCLK */
+	Native_M1, /* 75 GPO USB_OC1_B */
+	Native_M1, /* 76 PMU_RESETBUTTON_B */
+	GPIO_NC, /* 77 GPIO_ALERT */
+	Native_M1, /* 78 SDMMC3_PWR_EN_B */
+	Native_M1, /* 79 GPI ILB_SERIRQ */
+	Native_M1, /* 80 USB_OC0_B */
+	NATIVE_INT_PU20K(1, L1), /* 81 SDMMC3_CD_B */
+	Native_M1, /* 82 SPKR */
+	Native_M1, /* 83 SUSPWRDNACK */
+	SPARE_PIN, /* 84 spare pin */
+	Native_M1, /* 85 SDMMC3_1P8_EN */
+	GPIO_END
+};
+
+/* South West Community */
+static const struct soc_gpio_map  gpsw_gpio_map[] = {
+	NATIVE_PU20K(1), /* 00 FST_SPI_D2 */
+	NATIVE_PU20K(1), /* 01 FST_SPI_D0 */
+	NATIVE_PU20K(1), /* 02 FST_SPI_CLK */
+	NATIVE_PU20K(1), /* 03 FST_SPI_D3 */
+	NATIVE_PU20K(1), /* 04 FST_SPI_CS1_B */
+	NATIVE_PU20K(1), /* 05 FST_SPI_D1 */
+	NATIVE_PU20K(1), /* 06 FST_SPI_CS0_B */
+	GPIO_NC, /* 07 FST_SPI_CS2_B NC */
+	GPIO_NC, /* 15 UART1_RTS_B */
+	GPIO_NC, /* 16 UART1_RXD */
+	GPIO_NC, /* 17 UART2_RXD */
+	GPIO_NC, /* 18 UART1_CTS_B */
+	GPIO_NC, /* 19 UART2_RTS_B */
+	GPIO_NC, /* 20 UART1_TXD */
+	GPIO_NC, /* 21 UART2_TXD */
+	GPIO_NC, /* 22 UART2_CTS_B */
+	Native_M2, /* 30 MF_HDA_CLK */
+	Native_M2, /* 31 MF_HDA_RSTB */
+	Native_M2, /* 32 MF_HDA_SDI0 */
+	Native_M2, /* 33 MF_HDA_SDO */
+	GPIO_NC, /* 34 MF_HDA_DOCKRSTB */
+	Native_M2, /* 35 MF_HDA_SYNC */
+	GPIO_NC, /* 36 MF_HDA_SDI1 */
+	GPIO_NC, /* 37 MF_HDA_DOCKENB */
+	GPIO_NC, /* 45 I2C5_SDA */
+	GPIO_NC, /* 46 I2C4_SDA */
+	GPIO_INPUT_NO_PULL, /* 47 I2C6_SDA SD_WP_1P8*/
+	GPIO_NC, /* 48 I2C5_SCL */
+	GPIO_NC, /* 49 I2C_NFC_SDA */
+	GPIO_NC, /* 50 I2C4_SCL */
+	GPIO_NC, /* 51 I2C6_SCL */
+	GPIO_NC, /* 52 I2C_NFC_SCL */
+	GPIO_NC, /* 60 I2C1_SDA */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 61 I2C0_SDA */
+	GPIO_NC, /* 62 I2C2_SDA */
+	GPIO_NC, /* 63 I2C1_SCL */
+	GPIO_NC, /* 64 I2C3_SDA */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 65 I2C0_SCL */
+	GPIO_NC, /* 66 I2C2_SCL */
+	GPIO_NC, /* 67 I2C3_SCL */
+	GPIO_NC, /* 75 SATA_GP0 */
+	GPIO_NC, /* 76 GPI SATA_GP1 */
+	Native_M1, /* 77 SATA_LEDN */
+	GPIO_NC, /* 78 SATA_GP2 */
+	Native_M1, /* 79 MF_SMB_ALERT_N */
+	GPIO_INPUT_NO_PULL, /* 80 SATA_GP3, MMC1_RST */
+	Native_M1, /* 81 MF_SMB_CLK */
+	Native_M1, /* 82 MF_SMB_DATA */
+	Native_M1, /* 90 PCIE_CLKREQ0B */
+	Native_M1, /* 91 PCIE_CLKREQ1B */
+	GPIO_NC, /* 92 GP_SSP_2_CLK */
+	Native_M1, /* 93 PCIE_CLKREQ2B */
+	GPIO_NC, /* 94 GP_SSP_2_RXD */
+	Native_M1, /* 93 PCIE_CLKREQ3B */
+	GPIO_NC, /* 96 GP_SSP_2_FS */
+	GPIO_NC, /* 97 GP_SSP_2_TXD */
+	GPIO_END
+};
+
+/* North Community */
+static const struct soc_gpio_map  gpn_gpio_map[] = {
+	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
+	UNMASK_WAKE, SCI), /* 00 GPIO_DFX0 SMC_EXTSMI_N */
+	GPIO_NC, /* 01 GPIO_DFX3 */
+	GPIO_NC, /* 02 GPIO_DFX7 */
+	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
+	UNMASK_WAKE, SCI), /* 03 GPIO_DFX1 PM_THRM_N */
+	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
+	UNMASK_WAKE, SCI), /* 04 GPIO_DFX5 LID_N */
+	GPIO_NC, /* 05 GPIO_DFX4 */
+	GPIO_NC, /* 06 GPIO_DFX8 */
+	GPIO_NC, /* 07 GPIO_DFX2 */
+	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
+	UNMASK_WAKE, SCI), /* 08 GPIO_DFX6 WAKE1_N */
+	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
+	UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
+	GPIO_NC, /* 16 SEC_GPIO_SUS10 */
+	GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
+	/* 17 GPIO_SUS3 */
+	GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
+	/* 18 GPIO_SUS7 */
+	GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
+	/* 19 GPIO_SUS1 */
+	GPIO_NC, /* 20 GPIO_SUS5 */
+	GPIO_NC, /* 21 SEC_GPIO_SUS11 */
+	GPIO_NC, /* 22 GPIO_SUS4 */
+	GPIO_NC, /* 23 SEC_GPIO_SUS8 */
+	Native_M6, /* 24 GPIO_SUS2 */
+	GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */
+	Native_M1, /* 26 CX_PREQ_B */
+	GPIO_NC, /* 27 SEC_GPIO_SUS9 */
+	Native_M1, /* 30 TRST_B */
+	Native_M1, /* 31 TCK */
+	GPIO_SKIP, /* 32 PROCHOT_B */
+	GPIO_SKIP, /* 33 SVID0_DATA */
+	Native_M1, /* 34 TMS */
+	GPIO_NC, /* 35 CX_PRDY_B_2 */
+	GPIO_NC, /* 36 TDO_2 */
+	Native_M1, /* 37 CX_PRDY_B */
+	GPIO_SKIP, /* 38 SVID0_ALERT_B */
+	Native_M1, /* 39 TDO */
+	GPIO_SKIP, /* 40 SVID0_CLK */
+	Native_M1, /* 41 TDI */
+	GPIO_NC, /* 45 GP_CAMERASB05 */
+	GPIO_NC, /* 46 GP_CAMERASB02 */
+	Native_M2, /* 47 GP_CAMERASB08 */
+	GPIO_NC, /* 48 GP_CAMERASB00 */
+	GPIO_NC, /* 49 GP_CAMERASBO6 */
+	Native_M2, /* 50 GP_CAMERASB10 */
+	GPIO_NC, /* 51 GP_CAMERASB03 */
+	Native_M2, /* 52 GP_CAMERASB09 */
+	GPIO_NC, /* 53 GP_CAMERASB01 */
+	GPIO_NC, /* 54 GP_CAMERASB07 */
+	Native_M2, /* 55 GP_CAMERASB11 */
+	GPIO_NC, /* 56 GP_CAMERASB04 */
+	GPIO_NC, /* 60 PANEL0_BKLTEN */
+	Native_M1, /* 61 HV_DDI0_HPD */
+	GPIO_NC, /* 62 HV_DDI2_DDC_SDA */
+	GPIO_NC, /* 63 PANEL1_BKLTCTL */
+	Native_M1, /* 64 HV_DDI1_HPD */
+	Native_M1, /* 65 PANEL0_BKLTCTL */
+	NATIVE_PU20K(1), /* 66 HV_DDI0_DDC_SDA */
+	GPIO_NC, /* 67 HV_DDI2_DDC_SCL */
+	NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */
+	GPIO_NC, /* 69 PANEL1_VDDEN */
+	GPIO_NC, /* 70 PANEL1_BKLTEN */
+	NATIVE_PU20K(1), /* 71 HV_DDI0_DDC_SCL */
+	GPIO_NC, /* 72 PANEL0_VDDEN */
+	GPIO_END
+};
+
+/* East Community */
+static const struct soc_gpio_map  gpe_gpio_map[] = {
+	Native_M1, /* 00 PMU_SLP_S3_B */
+	GPIO_NC, /* 01 PMU_BATLOW_B */
+	Native_M1, /* 02 SUS_STAT_B */
+	Native_M1, /* 03 PMU_SLP_S0IX_B */
+	Native_M1, /* 04 PMU_AC_PRESENT */
+	Native_M1, /* 05 PMU_PLTRST_B */
+	Native_M1, /* 06 PMU_SUSCLK */
+	GPIO_NC, /* 07 PMU_SLP_LAN_B */
+	Native_M1, /* 08 PMU_PWRBTN_B */
+	Native_M1, /* 09 PMU_SLP_S4_B */
+	NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */
+	GPIO_NC, /* 11 PMU_WAKE_LAN_B */
+	GPIO_NC, /* 15 MF_GPIO_3 */
+	GPIO_NC, /* 16 MF_GPIO_7 */
+	GPIO_NC, /* 17 MF_I2C1_SCL */
+	GPIO_NC, /* 18 MF_GPIO_1 */
+	GPIO_NC, /* 19 MF_GPIO_5 */
+	GPIO_NC, /* 20 MF_GPIO_9 */
+	GPIO_NC, /* 21 MF_GPIO_0 */
+	GPIO_INPUT_PU_20K, /* 22 MF_GPIO_4 */
+	GPIO_NC, /* 23 MF_GPIO_8 */
+	GPIO_NC, /* 24 MF_GPIO_2 */
+	GPIO_NC, /* 25 MF_GPIO_6 */
+	GPIO_NC, /* 26 MF_I2C1_SDA */
+	GPIO_END
+};
+
+static struct soc_gpio_config gpio_config = {
+	/* BSW */
+	.north = gpn_gpio_map,
+	.southeast = gpse_gpio_map,
+	.southwest  = gpsw_gpio_map,
+	.east = gpe_gpio_map
+};
+
+struct soc_gpio_config *mainboard_get_gpios(void)
+{
+	return &gpio_config;
+}
diff --git a/src/mainboard/facebook/fbg1701/hda_verb.c b/src/mainboard/facebook/fbg1701/hda_verb.c
new file mode 100644
index 0000000000..344443f09a
--- /dev/null
+++ b/src/mainboard/facebook/fbg1701/hda_verb.c
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10EC0298,	/* Codec Vendor - Device ID: Realtek ALC298 */
+	0x152D1165,	/* Subsystem ID Quanta */
+	0x0000000C,	/* Number of jacks */
+
+	/* HDA Codec Subsystem ID Verb Table */
+	AZALIA_SUBVENDOR(0x0, 0x152D1165),
+
+	/* Pin Widget Verb Table */
+
+	/* Widget node 1 (NID 0x01) */
+	0x0017FF00,
+	0x0017FF00,
+	0x0017FF00,
+	0x0017FF00,
+
+	/* Pin Complex (NID 0x12) DMIC */
+	AZALIA_PIN_CFG(0x0, 0x12, 0x90A60130),
+
+	/* Pin Complex (NID 0x13) DMIC */
+	AZALIA_PIN_CFG(0x0, 0x13, 0x411111F0),
+
+	/* Pin Complex (NID 0x14) SPEAKER-OUT (Port-D) */
+	AZALIA_PIN_CFG(0x0, 0x14, 0x90180110),
+
+	/* Pin Complex (NID 0x17) I2S-OUT */
+	AZALIA_PIN_CFG(0x0, 0x17, 0x01011120),
+
+	/* Pin Complex (NID 0x18) MIC1 (Port-B) */
+	AZALIA_PIN_CFG(0x0, 0x18, 0x41111F0),
+
+	/* Pin Complex (NID 0x19) I2S-IN */
+	AZALIA_PIN_CFG(0x0, 0x19, 0x90870140),
+
+	/* Pin Complex (NID 0x1A) LINE1 (Port-C) */
+	AZALIA_PIN_CFG(0x0, 0x1A, 0x411111F0),
+
+	/* Pin Complex (NID 0x1D) PC-BEEP */
+	AZALIA_PIN_CFG(0x0, 0x1D, 0x40400001),
+
+	/* Pin Complex (NID 0x1E) SPDIF-OUT */
+	AZALIA_PIN_CFG(0x0, 0x1E, 0x411111F0),
+
+	/* Pin Complex (NID 0x1F) SPDIF-IN */
+	AZALIA_PIN_CFG(0x0, 0x1F, 0x411111F0),
+
+	/* Pin Complex (NID 0x21) HP-OUT (Port-A) */
+	AZALIA_PIN_CFG(0x0, 0x21, 0x411111F0),
+
+	/* POST I2S bypass output SRC */
+	0x0205002D,
+	0x0204C020,
+	0x0205002D,
+	0x0204C020,
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/facebook/fbg1701/irqroute.c b/src/mainboard/facebook/fbg1701/irqroute.c
new file mode 100644
index 0000000000..a4ff6bf2b2
--- /dev/null
+++ b/src/mainboard/facebook/fbg1701/irqroute.c
@@ -0,0 +1,18 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "irqroute.h"
+
+DEFINE_IRQ_ROUTES;
diff --git a/src/mainboard/facebook/fbg1701/irqroute.h b/src/mainboard/facebook/fbg1701/irqroute.h
new file mode 100644
index 0000000000..6b7cb4169e
--- /dev/null
+++ b/src/mainboard/facebook/fbg1701/irqroute.h
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2018 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/irq.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+
+/*
+ * IR02h GFX	INT(A)	- PIRQ A
+ * IR0Bh PUNIT	INT(A)	- PIRQ F
+ * IR10h EMMC	INT(ABCD)	- PIRQ DEFG
+ * IR11h SDIO	INT(A)	- PIRQ B
+ * IR12h SD	INT(A)	- PIRQ C
+ * IR13h SATA	INT(A)	- PIRQ D
+ * IR14h XHCI	INT(A)	- PIRQ E
+ * IR15h LP Audio	INT(A)	- PIRQ F
+ * IR17h MMC	INT(A)	- PIRQ F
+ * IR18h SIO	INT(ABCD)	- PIRQ BADC
+ * IR1Ah TXE	INT(A)	- PIRQ F
+ * IR1Bh HD Audio	INT(A)	- PIRQ G
+ * IR1Ch PCIe	INT(ABCD)	- PIRQ EFGH
+ * IR1Dh EHCI	INT(A)	- PIRQ D
+ * IR1Eh SIO	INT(ABCD)	- PIRQ BDEF
+ * IR1Fh LPC	INT(ABCD)	- PIRQ HGBC
+*/
+#define PCI_DEV_PIRQ_ROUTES \
+	PCI_DEV_PIRQ_ROUTE(GFX_DEV,    A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(PUNIT_DEV,  F, F, F, F), \
+	PCI_DEV_PIRQ_ROUTE(MMC_DEV,    D, E, F, G), \
+	PCI_DEV_PIRQ_ROUTE(SD_DEV,     C, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SATA_DEV,   D, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(XHCI_DEV,   E, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(LPE_DEV,    F, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SIO1_DEV,   B, A, D, C), \
+	PCI_DEV_PIRQ_ROUTE(TXE_DEV,    F, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(HDA_DEV,    G, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(PCIE_DEV,   E, F, G, H), \
+	PCI_DEV_PIRQ_ROUTE(SIO2_DEV,   B, D, E, F), \
+	PCI_DEV_PIRQ_ROUTE(PCU_DEV,    H, G, B, C)
+
+/*
+ * Route each PIRQ[A-H] to a PIC IRQ[0-15]
+ * Reserved: 0, 1, 2, 8, 13
+ * PS2 keyboard: 12
+ * ACPI/SCI: 9
+ * Floppy: 6
+ */
+#define PIRQ_PIC_ROUTES \
+	PIRQ_PIC(A, 11), \
+	PIRQ_PIC(B, 5), \
+	PIRQ_PIC(C, 5), \
+	PIRQ_PIC(D, 11), \
+	PIRQ_PIC(E, 11), \
+	PIRQ_PIC(F, 5), \
+	PIRQ_PIC(G, 11), \
+	PIRQ_PIC(H, 11)
diff --git a/src/mainboard/facebook/fbg1701/logo.c b/src/mainboard/facebook/fbg1701/logo.c
new file mode 100644
index 0000000000..678d2e2923
--- /dev/null
+++ b/src/mainboard/facebook/fbg1701/logo.c
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Patrick Rudolph <siro@das-labor.org>
+ * Copyright (C) 2018-2019 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/ramstage.h>
+#include <console/console.h>
+#include <include/cbfs.h>
+#include "mainboard.h"
+
+static char logo_data[1 * MiB];
+static size_t logo_data_sz = 0;
+
+void *load_logo(size_t *logo_size)
+{
+	const char *filename = "logo.bmp";
+
+	if (logo_data_sz != 0) {
+		if (logo_size)
+			*logo_size = logo_data_sz;
+		return (void *)logo_data;
+	}
+
+	logo_data_sz = cbfs_boot_load_file(filename, logo_data,
+				sizeof(logo_data), CBFS_TYPE_RAW);
+	if (logo_data_sz == 0)
+		return NULL;
+
+	if (logo_size)
+		*logo_size = logo_data_sz;
+
+	printk(BIOS_DEBUG, "Found a Logo of %zu bytes after decompression\n",
+		logo_data_sz);
+
+	return (void *)logo_data;
+}
diff --git a/src/mainboard/facebook/fbg1701/mainboard.c b/src/mainboard/facebook/fbg1701/mainboard.c
new file mode 100644
index 0000000000..ff2564d67a
--- /dev/null
+++ b/src/mainboard/facebook/fbg1701/mainboard.c
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2018-2019 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include "onboard.h"
+#include "mainboard.h"
+
+/*
+ * Declare the resources we are using
+ */
+static void mainboard_reserve_resources(struct device *dev)
+{
+	unsigned int idx = 0;
+	struct resource *res;
+
+	/*
+	 * CPLD: Reserve the IRQ here all others are within the default LPC
+	 * range 0 to 1000h
+	 */
+	res = new_resource(dev, idx++);
+	res->base = 0x7;
+	res->size = 0x1;
+	res->flags = IORESOURCE_IRQ | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+/*
+ * mainboard_enable is executed as first thing after
+ * enumerate_buses().
+ */
+static void mainboard_enable(struct device *dev)
+{
+	mainboard_reserve_resources(dev);
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/facebook/fbg1701/mainboard.h b/src/mainboard/facebook/fbg1701/mainboard.h
new file mode 100644
index 0000000000..e161da0396
--- /dev/null
+++ b/src/mainboard/facebook/fbg1701/mainboard.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_H
+#define MAINBOARD_H
+
+void *load_logo(size_t *logo_size);
+
+#endif
diff --git a/src/mainboard/facebook/fbg1701/onboard.h b/src/mainboard/facebook/fbg1701/onboard.h
new file mode 100644
index 0000000000..d1fd0509a6
--- /dev/null
+++ b/src/mainboard/facebook/fbg1701/onboard.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2018-2019 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+/* SD CARD gpio */
+#define SDCARD_CD		81 /* Not used */
+
+#define ITE8528_CMD_PORT	0x6E
+#define ITE8528_DATA_PORT	0x6F
+
+/* CPLD definitions */
+#define CPLD_PCB_VERSION_PORT 0x283
+#define CPLD_PCB_VERSION_MASK 0xF0
+#define CPLD_PCB_VERSION_BIT  4
+
+#define CPLD_RESET_PORT 0x287
+#define CPLD_CMD_RESET_DSI_BRIDGE_ACTIVE 0x20
+#define CPLD_CMD_RESET_DSI_BRIDGE_INACTIVE 0x00
+
+#endif
diff --git a/src/mainboard/facebook/fbg1701/ramstage.c b/src/mainboard/facebook/fbg1701/ramstage.c
new file mode 100644
index 0000000000..91dfe3b2cf
--- /dev/null
+++ b/src/mainboard/facebook/fbg1701/ramstage.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018-2019 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/ramstage.h>
+#include "mainboard.h"
+
+void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
+{
+	if (CONFIG(FSP1_1_DISPLAY_LOGO)) {
+		size_t logo_len;
+		void *logo = NULL;
+
+		logo = load_logo(&logo_len);
+
+		if (logo) {
+			params->PcdLogoPtr = (u32)logo;
+			params->PcdLogoSize = logo_len;
+		}
+	}
+}
diff --git a/src/mainboard/facebook/fbg1701/romstage.c b/src/mainboard/facebook/fbg1701/romstage.c
new file mode 100644
index 0000000000..e2e37d6387
--- /dev/null
+++ b/src/mainboard/facebook/fbg1701/romstage.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2018-2019 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbfs.h>
+#include <console/console.h>
+#include <chip.h>
+#include <device/pci_ops.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
+#include <spd_bin.h>
+#include <stdint.h>
+
+void mainboard_memory_init_params(struct romstage_params *params,
+	MEMORY_INIT_UPD *memory_params)
+{
+	struct region_device spd_rdev;
+	u8 spd_index = 0;
+
+	if (CONFIG(ONBOARD_MICRON_MEM))
+		spd_index = 1;
+	if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0)
+		die("spd.bin not found\n");
+
+	memory_params->PcdMemoryTypeEnable = MEM_DDR3;
+	memory_params->PcdMemorySpdPtr = (uintptr_t)rdev_mmap_full(&spd_rdev);
+	memory_params->PcdMemChannel0Config = 1; /* Memory down */
+	memory_params->PcdMemChannel1Config = 2; /* Disabled */
+}
+
+void mainboard_after_memory_init(void)
+{
+	printk(BIOS_DEBUG, "%s/%s called\n", __FILE__, __func__);
+
+	/* Disable the Braswell UART hardware for COM1. */
+	pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, 0);
+}
diff --git a/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex b/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex
new file mode 100644
index 0000000000..f18cbc2a87
--- /dev/null
+++ b/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex
@@ -0,0 +1,257 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2019 Eltan B.V.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+#
+# 8 Gb DDR3 (1600 MHz 11-11-11) Micron MT41K512M16HA-125:A
+#
+# SINGLE DIE
+#
+
+# 512MBx16 64Mx16x8 ( 8 bank, 16 Rows, 10 Col, 2 KB page size )
+# 5-6-7-8-9-10-11
+# DDR3L-1600
+# tCk 1.25ns
+# tRCD 13.75ns
+# tRP 13.75ns
+# tRAS 35ns
+# tRC 48.75ns
+# CL-tRCD-tRP 11-11-11
+
+#	0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
+#		bits[3:0]: 3 = 384 SPD Bytes Used
+#		bits[6:4]: 1 = 256 SPD Bytes Total
+#		bit7 : 0 = CRC covers bytes 0 ~ 128
+23
+
+#	1 SPD Revision
+#		0x10 = Revision 1.0
+10
+
+#	2 Key Byte / DRAM Device Type
+#		bits[7:0]: 0x0c = DDR3 SDRAM
+0B
+
+#	3 Key Byte / Module Type
+#		bits[3:0]: 3 = SODIMM
+#		bits[6:4]: 0 = Not hybrid
+#		bits[7]: 0 = Not hybrid
+03
+
+#	4 SDRAM CHIP Density and Banks
+#		bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip
+#		bits[6:4]: 0 = 3 (8 banks)
+#		bits[7]: reserverd
+05
+
+#	5 SDRAM Addressing
+#		bits[2:0]: 1 = 10 Column Address Bits
+#		bits[5:3]: 4 = 16 Row Address Bits
+#		bits[7:6]: 0 = reserved
+21
+
+#	6 Module Nominal Voltage
+#		bits[0]: 0 = 1.5V operable
+#		bits[1]: 1 = 1.35V operable
+#		bits[2]: 0 = NOT 1.25V operable
+#		bits[7:3]: reserved
+02
+
+#	7 Module Organization
+#		bits[2:0]: 010b = 16 bits SDRAM device
+#		bits[5:3]: 000b = 1 ranks
+#		bits[7:6]: reserved
+02
+
+#	8 Module Memory Bus width
+#		bits[2:0]: 3 = 64 bits pirmary bus width
+#		bits[4:3]: 0 = 0 bits bus witdth extension
+#		bits[7:5]: reserved
+03
+
+#	9 Fine Timebase (FTB) dividend / divisor
+#		bits[3:0]: 1 = Divisor
+#		bits[7:4]: 1 = Dividend
+11
+
+#	10 Medium Timebase (MTB) dividend
+#		bits[7:0]: 0 = 1 (timebase 0.125ns)
+01
+
+#	11 Medium Timebase (MTB) divisor
+#		bits[7:0]: 8 (timebase 0.125ns)
+08
+
+#	12 SDRAM Minimum cycle time (tCKmin)
+#		0xA tCK = 1.25ns (DDR3-1600 (800 MHz clock))
+0A
+
+#	13 Reserved
+00
+
+#	14 CAS Latencies supported, Least Significate Byte
+#		Support 5,6,7,8,9,10,11
+FE
+
+#	15 CAS Latencies supported, Most Significate Byte
+#		No supporting CL 12-18
+00
+
+#	16 Minimum CAS Latency Time (tAAmin)
+#		0x69 tAA = 13.125ns (offset = 00) DDR3-1600K downbin
+69
+
+#	17 Minimum Write Recovery Time (tWRmin)
+#		0x78 tWR = 15 ns
+78
+
+#	18 Minimum RAS to CAS Delay Time (tRCDmin)
+#		0x69 tRCD = 13.125ns (offset 00) DDR3-1600K downbin
+69
+
+#	19 Minimum Row Active to Row Active Delay Time (tRRDmin)
+#		0x3C tRRD = 7.5ns DDR3-1600, 2KB
+3C
+
+#	20 Minimum Row Precharge Delay Time (tRPmin)
+#		0x69 tRP = 13.125ns (offset 00) DDR3-1600K downbin
+69
+
+#	21 Upper Nibble for tRAS and tRC
+#		3:0 : 1 higher tRAS = 35ns
+#		7:0 : 1 higher tRC = 48.125ns
+11
+
+#	22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant byte
+#		lower 0x118 : tRAS = 35ns DDR3-1600
+18
+
+#	23 Minimum Active to Precharge Delay Time (tRCmin), Most Significant byte
+#		lower 0x181 : tRC = 48.125ns  (offset 00) DDR3-1600K downbin
+81
+
+#	24 Minimum Refresh Recovery Delay time (tRFCmin), Least Significant byte
+#		lower 0xAF0 : tRFC = 350ns 8 Gb
+F0
+
+#	25 Minimum Refresh Recovery Delay time (tRFCmin), Most Significant byte
+#		higher 0xAF0 : tRFC = 350ns 8 Gb
+0A
+
+#	26 tWTRmin
+#		0x3C : tWTR = 7.5 ns (DDR3)
+3C
+
+#	27 tRTPmin
+#		0x3C : tRTP = 7.5 ns (DDR3)
+3C
+
+#	28 Upper Nibble for tFAW
+#		Bit [3:0] : 1 = higher 0x140 tFAW = 40ns
+01
+
+#	29 tFAWmin Lower
+#		lower 0x140 : tFAW = 40ns
+40
+
+#	30 SDRAM Optional Features
+#		byte [0] : 1 = RZQ/6 is support
+#		byte [1] : 1 = RZQ/7 is supported
+#		byte [7] : 1 = DLL-Off Mode support
+83
+
+#	31 Thermal options
+#		byte [0] : 1 = 0 - 95C
+#		byte [2] : 1 = Auto Self Refresh (ASR) is supported
+#		byte [7] : 1 = Partial Array Self Refres (PASR) is supported
+85
+
+#	32 Module Thermal support
+#		byte [0] : 0 = Thermal sensor accuracy undefined
+#		byte [7] : 0 = No thermal sensor
+00
+
+#	33 SDRAM device type
+# 		byte [1:0] : 00b = Signal Loading not specified
+#		byte [6:4] : 000b = Die count not specified
+#		byte [7]   : 1 = Non-Standard Device
+80
+
+#	34 Fine tCKmin
+#		0x00 tCK = 1.25ns (DDR3-1600 (800 MHz clock))
+00
+
+#	35 Fine tAAmin
+#		0x00 tAA = 13.125ns (tAAmin offset = 00) DDR3-1600K downbin
+00
+
+#	36 Fine tRCDmin
+#		0x00 tRCD = 13.125ns DDR3-1600K downbin
+00
+
+#	37 Fine tRPmin
+#		0x00 tRP = 13.125ns (offset 00) DDR3-1600K downbin
+00
+
+#	38 Fine tRCmin
+#		0x00 tRC = 48.125ns (offset 00) DDR3-1600K downbin
+00
+
+#	39-59 reserved, general section
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00
+
+#	60-116 Module specific section
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00
+
+#	117-118 Module Manufacturer
+80 2C
+
+#	119 Module Manufacturing Location
+01
+
+#	120-121 Module Manufacturing Date
+13 0A
+
+#	122-125 Module Serial number
+00 00 00 00
+
+#	126-127 SPD CRC
+00 00
+
+#	128-145 Module Part number
+4D 54 34 31 4B 35 31 32 4D 31 36 48 41 2D 31 32
+35 00
+
+#	145-146 Module revision code
+00 00
+
+#	148-149 DRAM Manufacturer ID code
+80 2C
+
+#	150-175 Manufacturer Specific Data
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00
+
+#	176-255 Open for Customer Use
+
+#	176 - 255
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex b/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex
new file mode 100644
index 0000000000..64faf1e163
--- /dev/null
+++ b/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex
@@ -0,0 +1,254 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2018-2019 Eltan B.V.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+#
+# 8 Gb DDR3 (1600 MHz 11-11-11) Samsung K4B8G1646D-MYK0
+#
+# DUAL DIE
+#
+# 512Mb x16 ( 8 bank, 16 Rows, 10 Col, 2 KB page size )
+# 5-6-7-8-9-10-11
+# DDR3L-1600
+# tCk 1.25ns
+# tRCD 13.75ns
+# tRP 13.75ns
+# tRAS 35ns
+# tRC 48.75ns
+# CL-tRCD-tRP 11-11-11
+
+#	0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
+#		bits[3:0]: 3 = 384 SPD Bytes Used
+#		bits[6:4]: 1 = 256 SPD Bytes Total
+#		bit7 : 0 = CRC covers bytes 0 ~ 128
+23
+
+#	1 SPD Revision
+#		0x10 = Revision 1.0
+10
+
+#	2 Key Byte / DRAM Device Type
+#		bits[7:0]: 0x0c = DDR3 SDRAM
+0B
+
+#	3 Key Byte / Module Type
+#		bits[3:0]: 3 = SODIMM
+#		bits[6:4]: 0 = Not hybrid
+#		bits[7]: 0 = Not hybrid
+03
+
+#	4 SDRAM CHIP Density and Banks
+#		bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
+#		bits[6:4]: 0 = 3 (8 banks)
+#		bits[7]: reserverd
+04
+
+#	5 SDRAM Addressing
+#		bits[2:0]: 1 = 10 Column Address Bits
+#		bits[5:3]: 100b = 16 Row Address Bits
+#		bits[7:6]: 0 = reserved
+21
+
+#	6 Module Nominal Voltage
+#		bits[0]: 0 = 1.5V operable
+#		bits[1]: 1 = 1.35V operable
+#		bits[2]: 0 = NOT 1.25V operable
+#		bits[7:3]: reserved
+02
+
+#	7 Module Organization
+#		bits[2:0]: 010b = 16 bits SDRAM device
+#		bits[5:3]: 001b = 2 ranks
+#		bits[7:6]: reserved
+0A
+
+#	8 Module Memory Bus width
+#		bits[2:0]: 3 = 64 bits pirmary bus width
+#		bits[4:3]: 0 = 0 bits bus witdth extension
+#		bits[7:5]: reserved
+03
+
+#	9 Fine Timebase (FTB) dividend / divisor
+#		bits[3:0]: 1 = Divisor
+#		bits[7:4]: 1 = Dividend
+11
+
+#	10 Medium Timebase (MTB) dividend
+#		bits[7:0]: 0 = 1 (timebase 0.125ns)
+01
+
+#	11 Medium Timebase (MTB) divisor
+#		bits[7:0]: 8 (timebase 0.125ns)
+08
+
+#	12 SDRAM Minimum cycle time (tCKmin)
+#		0xA tCK = 1.25ns (DDR3-1600 (800 MHz clock))
+0A
+
+#	13 Reserved
+00
+
+#	14 CAS Latencies supported, Least Significate Byte
+#		Support 5,6,7,8,9,10,11
+FE
+
+#	15 CAS Latencies supported, Most Significate Byte
+#		Not supporting CL 12-18
+00
+
+#	16 Minimum CAS Latency Time (tAAmin)
+#		0x69 tAA = 13.125ns (offset = 00) DDR3-1600K downbin
+69
+
+#	17 Minimum Write Recovery Time (tWRmin)
+#		0x78 tWR = 15 ns
+78
+
+#	18 Minimum RAS to CAS Delay Time (tRCDmin)
+#		0x69 tRCD = 13.125ns (offset 00) DDR3-1600K downbin
+69
+
+#	19 Minimum Row Active to Row Active Delay Time (tRRDmin)
+#		48 tRRD = 6.0ns DDR3-1600, 1KB
+30
+
+#	20 Minimum Row Precharge Delay Time (tRPmin)
+#		0x69 tRP = 13.125ns (offset 00) DDR3-1600K downbin
+69
+
+#	21 Upper Nibble for tRAS and tRC
+#		3:0 : 1 higher tRAS = 35ns
+#		7:0 : 1 higher tRC = 48.125ns
+11
+
+#	22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant byte
+#		lower 0x118 : tRAS = 35ns DDR3-1600
+18
+
+#	23 Minimum Active to Precharge Delay Time (tRCmin), Most Significant byte
+#		lower 0x181 : tRC = 48.125ns  (offset 00) DDR3-1600K downbin
+81
+
+#	24 Minimum Refresh Recovery Delay time (tRFCmin), Least Significant byte
+#		lower 0x680 : tRFC = 208ns 4 Gb
+80
+
+#	25 Minimum Refresh Recovery Delay time (tRFCmin), Most Significant byte
+#		higher 0x680 : tRFC = 208ns 4 Gb
+06
+
+#	26 tWTRmin
+#		0x3C : tWTR = 7.5 ns (DDR3)
+3C
+
+#	27 tRTPmin
+#		0x3C : tRTP = 7.5 ns (DDR3)
+3C
+
+#	28 Upper Nibble for tFAW
+#		Bit [3:0] : 1 = higher 0x140 tFAW = 40ns DDR3-1600K, 2 KB page size
+01
+
+#	29 tFAWmin Lower
+#		lower 0x140 : tFAW = 40ns DDR3-1600K, 2 KB page size
+40
+
+#	30 SDRAM Optional Features
+#		byte [0] : 1 = RZQ/6 is support
+#		byte [1] : 1 = RZQ/7 is supported
+#		byte [7] : 1 = DLL-Off Mode support
+83
+
+#	31 Thermal options
+#		byte [2]: 1 = Auto Self Refresh (ASR) is supported
+04
+
+#	32 Module Thermal support
+#		byte [0] : 0 = Thermal sensor accuracy undefined
+#		byte [7] : 0 = No thermal sensor
+00
+
+#	33 SDRAM device type
+#		byte [1:0] : 01b = multi load stack
+# 		byte [6:4] : 100b = 8 die
+#		byte [7]   : 0 = Standard Device
+41
+
+#	34 Fine tCKmin
+#		0x00 tCK = 1.25ns (DDR3-1600 (800 MHz clock))
+00
+
+#	35 Fine tAAmin
+#		0x00 tAA = 13.125ns (tAAmin offset = 00) DDR3-1600K downbin
+00
+
+#	36 Fine tRCDmin
+#		0x00 tRCD = 13.125ns DDR3-1600K downbin
+00
+
+#	37 Fine tRPmin
+#		0x00 tRP = 13.125ns (offset 00) DDR3-1600K downbin
+00
+
+#	38 Fine tRCmin
+#		0x00 tRC = 48.125ns (offset 00) DDR3-1600K downbin
+00
+
+#	39-59 reserved, general section
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00
+
+#	60-116 Module specific section
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00
+
+#	117-118 Module Manufacturer
+80 CE
+
+#	119 Module Manufacturing Location
+01
+
+#	120-121 Module Manufacturing Date
+12 1B
+
+#	122-125 Module Serial number
+00 00 00 00
+
+#	126-127 SPD CRC
+00 00
+
+#	128-145 Module Part number
+4B 34 42 38 47 31 36 34 36 44 2D 4D 59 4B 30 20
+20 20
+
+#	145-146 Module revision code
+00 00
+
+#	148-149 DRAM Manufacturer ID code
+80 CE
+
+#	150-175 Manufacturer Specific Data
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00
+
+#	176-255 Open for Customer Use
+
+#	176 - 255
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/facebook/fbg1701/w25q64.c b/src/mainboard/facebook/fbg1701/w25q64.c
new file mode 100644
index 0000000000..bc908f04b3
--- /dev/null
+++ b/src/mainboard/facebook/fbg1701/w25q64.c
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2018 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/spi.h>
+#include <string.h>
+#include <drivers/spi/spi_winbond.h>
+
+/*
+ * SPI lockdown configuration
+ */
+#define SPI_OPMENU_0	CMD_W25_WRSR		/* Write Status Register */
+#define SPI_OPTYPE_0	SPI_OPTYPE_WR_NOADDR	/* Write, no address */
+
+#define SPI_OPMENU_1	CMD_W25_PP		/* BYPR: Byte Program */
+#define SPI_OPTYPE_1	SPI_OPTYPE_WR_ADDR	/* Write, address required */
+
+#define SPI_OPMENU_2	CMD_W25_READ		/* Read Data */
+#define SPI_OPTYPE_2	SPI_OPTYPE_RD_ADDR	/* Read, address required */
+
+#define SPI_OPMENU_3	CMD_W25_RDSR		/* Read Status Register */
+#define SPI_OPTYPE_3	SPI_OPTYPE_RD_NOADDR	/* Read, no address */
+
+#define SPI_OPMENU_4	CMD_W25_SE		/* Sector Erase */
+#define SPI_OPTYPE_4	SPI_OPTYPE_WR_ADDR	/* Write, address required */
+
+#define SPI_OPMENU_5	CMD_W25_RDID		/* Read ID */
+#define SPI_OPTYPE_5	SPI_OPTYPE_RD_NOADDR	/* Read, no address */
+
+#define SPI_OPMENU_6	CMD_W25_BE		/* BE: Block Erase */
+#define SPI_OPTYPE_6	SPI_OPTYPE_WR_ADDR	/* Write, address required */
+
+#define SPI_OPMENU_7	CMD_W25_FAST_READ	/* FAST: Fast Read */
+#define SPI_OPTYPE_7	SPI_OPTYPE_RD_ADDR	/* Read, address required */
+
+#define SPI_OPPREFIX	CMD_W25_WREN		/* WREN only to be inline */
+						/* with flashrom */
+
+#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
+		    (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 <<  8) | \
+		    (SPI_OPTYPE_3 <<  6) | (SPI_OPTYPE_2 <<  4) | \
+		    (SPI_OPTYPE_1 <<  2) | (SPI_OPTYPE_0 <<  0))
+
+#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
+			  (SPI_OPMENU_5 <<  8) | (SPI_OPMENU_4 <<  0))
+
+#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
+			  (SPI_OPMENU_1 <<  8) | (SPI_OPMENU_0 <<  0))
+
+#define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB)
+
+static const struct spi_config spi_config = {
+	.preop = CMD_W25_WREN,
+	.optype = SPI_OPTYPE,
+	.opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER },
+	.lvscc =  SPI_VSCC,
+	.uvscc =  SPI_VSCC,
+};
+
+int mainboard_get_spi_config(struct spi_config *cfg)
+{
+	memcpy(cfg, &spi_config, sizeof(*cfg));
+
+	return 0;
+}