soc/amd/cezanne: Enable early LPC support in bootblock stage

Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I739d97ddc5afd84a4bbc7e505b423158eb820767
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

5 files changed, 27 insertions, 0 deletions

diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 611260d829..a881ef802d 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -24,6 +24,7 @@ config SOC_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
 	select SOC_AMD_COMMON_BLOCK_AOAC
 	select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
+	select SOC_AMD_COMMON_BLOCK_LPC
 	select SOC_AMD_COMMON_BLOCK_NONCAR
 	select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
 	select SOC_AMD_COMMON_BLOCK_PSP_GEN2
diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c
index 37ba4c7a1a..8353cb155e 100644
--- a/src/soc/amd/cezanne/early_fch.c
+++ b/src/soc/amd/cezanne/early_fch.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/acpimmio.h>
+#include <amdblocks/lpc.h>
 #include <amdblocks/smbus.h>
 #include <console/console.h>
 #include <soc/southbridge.h>
@@ -9,6 +10,8 @@
 /* Before console init */
 void fch_pre_init(void)
 {
+	lpc_early_init();
+
 	enable_acpimmio_decode_pm04();
 	fch_smbus_init();
 	fch_enable_cf9_io();
diff --git a/src/soc/amd/cezanne/include/soc/acpi.h b/src/soc/amd/cezanne/include/soc/acpi.h
new file mode 100644
index 0000000000..6927d93cff
--- /dev/null
+++ b/src/soc/amd/cezanne/include/soc/acpi.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef AMD_CEZANNE_ACPI_H
+#define AMD_CEZANNE_ACPI_H
+
+
+#endif /* AMD_CEZANNE_ACPI_H */
diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h
index b91ff2785b..73640f5ab9 100644
--- a/src/soc/amd/cezanne/include/soc/iomap.h
+++ b/src/soc/amd/cezanne/include/soc/iomap.h
@@ -4,6 +4,7 @@
 #define AMD_CEZANNE_IOMAP_H
 
 /* MMIO Ranges */
+#define SPI_BASE_ADDRESS		0xfec10000
 /* FCH AL2AHB Registers */
 #define ALINK_AHB_ADDRESS		0xfedc0000
 
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h
index 8623063140..9353e13ace 100644
--- a/src/soc/amd/cezanne/include/soc/southbridge.h
+++ b/src/soc/amd/cezanne/include/soc/southbridge.h
@@ -8,6 +8,17 @@
 /* Power management registers:  0xfed80300 or index/data at IO 0xcd6/cd7 */
 #define PWR_RESET_CFG			0x10
 #define   TOGGLE_ALL_PWR_GOOD		(1 << 1)
+#define PM_SERIRQ_CONF			0x54
+#define   PM_SERIRQ_NUM_BITS_17		0x0000
+#define   PM_SERIRQ_NUM_BITS_18		0x0004
+#define   PM_SERIRQ_NUM_BITS_19		0x0008
+#define   PM_SERIRQ_NUM_BITS_20		0x000c
+#define   PM_SERIRQ_NUM_BITS_21		0x0010
+#define   PM_SERIRQ_NUM_BITS_22		0x0014
+#define   PM_SERIRQ_NUM_BITS_23		0x0018
+#define   PM_SERIRQ_NUM_BITS_24		0x001c
+#define   PM_SERIRQ_MODE		BIT(6)
+#define   PM_SERIRQ_ENABLE		BIT(7)
 #define PM_EVT_BLK			0x60
 #define   WAK_STS			BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */
 #define   PCIEXPWAK_STS			BIT(14)
@@ -39,6 +50,10 @@
 #define   PM_ACPI_WAKE_AS_GEVENT	BIT(27)
 #define   PM_ACPI_NB_PME_GEVENT		BIT(28)
 #define   PM_ACPI_RTC_WAKE_EN		BIT(29)
+#define PM_LPC_GATING			0xec
+#define   PM_LPC_AB_NO_BYPASS_EN	BIT(2)
+#define   PM_LPC_A20_EN			BIT(1)
+#define   PM_LPC_ENABLE			BIT(0)
 
 #define FCH_LEGACY_UART_DECODE		(ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */