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authorMarc Jones <marc.jones@amd.com>2008-09-23 22:19:27 +0000
committerMarc Jones <marc.jones@amd.com>2008-09-23 22:19:27 +0000
commit3aca4b5734e13dc5a40d238421be8c0f072ee552 (patch)
tree6f1b98f3b90dca3aebda680f02f11c5c4feb435e
parent0f4282b538213c17913821bc8e84877074838edf (diff)
The AMD dbm690t mainboard uses the it8712f SIO with the
default 48MHz clock input. The Asus a8n_e uses the it8712f with a 24MHz clock input. The it8712f early init code was setting a 24MHz input clock(to support the a8n_e). Since 48Mhz is the default I added a function to set 24MHz input clock to the a8n_e. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r--src/mainboard/asus/a8n_e/cache_as_ram_auto.c1
-rw-r--r--src/superio/ite/it8712f/it8712f_early_serial.c38
2 files changed, 31 insertions, 8 deletions
diff --git a/src/mainboard/asus/a8n_e/cache_as_ram_auto.c b/src/mainboard/asus/a8n_e/cache_as_ram_auto.c
index 41af6ca528..5f8e93ba4e 100644
--- a/src/mainboard/asus/a8n_e/cache_as_ram_auto.c
+++ b/src/mainboard/asus/a8n_e/cache_as_ram_auto.c
@@ -221,6 +221,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
bsp_apicid = init_cpus(cpu_init_detectedx);
}
+ it8712f_24mhz_clkin();
it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
diff --git a/src/superio/ite/it8712f/it8712f_early_serial.c b/src/superio/ite/it8712f/it8712f_early_serial.c
index 7839732787..dd84245dc4 100644
--- a/src/superio/ite/it8712f/it8712f_early_serial.c
+++ b/src/superio/ite/it8712f/it8712f_early_serial.c
@@ -45,10 +45,10 @@ static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
outb(value, SIO_DATA);
}
-/* Enable the peripheral devices on the IT8712F Super I/O chip. */
-static void it8712f_enable_serial(device_t dev, unsigned iobase)
+
+static void it8712f_enter_conf(void)
{
- /* (1) Enter the configuration state (MB PnP mode). */
+ /* Enter the configuration state (MB PnP mode). */
/* Perform MB PnP setup to put the SIO chip at 0x2e. */
/* Base address 0x2e: 0x87 0x01 0x55 0x55. */
@@ -57,6 +57,32 @@ static void it8712f_enable_serial(device_t dev, unsigned iobase)
outb(0x01, IT8712F_CONFIGURATION_PORT);
outb(0x55, IT8712F_CONFIGURATION_PORT);
outb(0x55, IT8712F_CONFIGURATION_PORT);
+}
+
+static void it8712f_exit_conf(void)
+{
+ /* Exit the configuration state (MB PnP mode). */
+ it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02);
+}
+
+
+static void it8712f_24mhz_clkin(void)
+{
+ it8712f_enter_conf();
+
+ /* Select 24MHz CLKIN (48MHZ default)*/
+ it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x1);
+
+ it8712f_exit_conf();
+
+}
+
+/* Enable the peripheral devices on the IT8712F Super I/O chip. */
+static void it8712f_enable_serial(device_t dev, unsigned iobase)
+{
+
+ /* (1) Enter the configuration state (MB PnP mode). */
+ it8712f_enter_conf();
/* (2) Modify the data of configuration registers. */
@@ -69,13 +95,9 @@ static void it8712f_enable_serial(device_t dev, unsigned iobase)
it8712f_sio_write(IT8712F_SP1, 0x30, 0x1); /* Serial port 1 */
it8712f_sio_write(IT8712F_SP2, 0x30, 0x1); /* Serial port 2 */
- /* Select 24MHz CLKIN (set bit 0). */
- it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x01);
-
/* Clear software suspend mode (clear bit 0). TODO: Needed? */
/* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_SWSUSP, 0x00); */
/* (3) Exit the configuration state (MB PnP mode). */
- it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02);
+ it8712f_exit_conf();
}
-