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authorWisley Chen <wisley.chen@quantatw.com>2016-11-10 09:44:13 -0500
committerAaron Durbin <adurbin@chromium.org>2016-11-11 16:14:24 +0100
commit232d31899be8d09db1a32052114e87526d00a057 (patch)
treedec5b0306273726acb93e3ba611a187b713b6fea
parent4668ba77eaf0418eac37fe67ba06a450d3eafe88 (diff)
mainboard/google/snappy: Set PL1 override to 12000mW
Snappy is using APL SoC SKU's with 6W TDP max. As Reef, the energy calculation is wrong with the current VR solution. Experiments show that SoC TDP max (6W) can be reached when RAPL PL1 is set to 12W. Therefore, we've inserted 12W override after reading the fused value (6W) so that the system can reach the right performance level. BUG=chrome-os-partner:59034 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: Idd702077cd05e2b43823542cb804b2d4b42f7116 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17362 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
-rw-r--r--src/mainboard/google/reef/variants/snappy/devicetree.cb5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb
index 43ec2ed054..b4c53ea70e 100644
--- a/src/mainboard/google/reef/variants/snappy/devicetree.cb
+++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb
@@ -49,6 +49,11 @@ chip soc/intel/apollolake
# Enable DPTF
register "dptf_enable" = "1"
+ # PL1 override 12000 mW: the energy calculation is wrong with the
+ # current VR solution. Experiments show that SoC TDP max (6W) can
+ # be reached when RAPL PL1 is set to 12W.
+ register "tdp_pl1_override_mw" = "12000"
+
# Enable Audio Clock and Power gating
register "hdaudio_clk_gate_enable" = "1"
register "hdaudio_pwr_gate_enable" = "1"