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authorMarshall Dawson <marshalldawson3rd@gmail.com>2019-05-02 18:56:54 -0600
committerPatrick Georgi <pgeorgi@google.com>2019-05-06 10:33:03 +0000
commit1bc04e3c3edf5b1537b4846dea41a530a1b83016 (patch)
tree73fd539a3d764568f6144ff1246b45caf05aabf8
parente09caf6428bbda556df7089a46abcf7dd26bb3a3 (diff)
soc/amd/stoneyridge: Correct bugs in lpc.c
Remove the bridge enable step of accessing D14F0x64. This method for enabling the bridge appears to be last present in the SB700 device. Beginning in the SB800 (and all FCH, SoC devices), the enable is in PMxEC[0]. Since the bridge is enabled in bootblock to allow port 80h, there is no need to maintain it in ramstage. Correct the device used for misc. configuration of the LPC bridge. The #defined value removed is 14.0 but the settings are in 14.3. TEST=Boot Grunt, check console and dmesg for errors and warnings BUG=b:131862871 Change-Id: I078be974dc3c78c94cb7c0832518f21bac029ff2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
-rw-r--r--src/soc/amd/stoneyridge/lpc.c39
1 files changed, 13 insertions, 26 deletions
diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c
index 9a8c8efdee..a838146c84 100644
--- a/src/soc/amd/stoneyridge/lpc.c
+++ b/src/soc/amd/stoneyridge/lpc.c
@@ -35,31 +35,22 @@
static void lpc_init(struct device *dev)
{
u8 byte;
- u32 dword;
-
- /*
- * Enable the LPC Controller
- * SMBus register 0x64 is not defined in public datasheet.
- */
- dword = pci_read_config32(SOC_SMBUS_DEV, 0x64);
- dword |= 1 << 20;
- pci_write_config32(SOC_SMBUS_DEV, 0x64, dword);
/* Initialize isa dma */
isa_dma_init();
/* Enable DMA transaction on the LPC bus */
- byte = pci_read_config8(SOC_SMBUS_DEV, LPC_PCI_CONTROL);
+ byte = pci_read_config8(dev, LPC_PCI_CONTROL);
byte |= LEGACY_DMA_EN;
- pci_write_config8(SOC_SMBUS_DEV, LPC_PCI_CONTROL, byte);
+ pci_write_config8(dev, LPC_PCI_CONTROL, byte);
/* Disable the timeout mechanism on LPC */
- byte = pci_read_config8(SOC_SMBUS_DEV, LPC_IO_OR_MEM_DECODE_ENABLE);
+ byte = pci_read_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
byte &= ~LPC_SYNC_TIMEOUT_COUNT_ENABLE;
- pci_write_config8(SOC_SMBUS_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, byte);
+ pci_write_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE, byte);
/* Disable LPC MSI Capability */
- byte = pci_read_config8(SOC_SMBUS_DEV, LPC_MISC_CONTROL_BITS);
+ byte = pci_read_config8(dev, LPC_MISC_CONTROL_BITS);
/* BIT 1 is not defined in public datasheet. */
byte &= ~(1 << 1);
@@ -69,15 +60,15 @@ static void lpc_init(struct device *dev)
* interrupt and visit LPC.
*/
byte &= ~LPC_NOHOG;
- pci_write_config8(SOC_SMBUS_DEV, LPC_MISC_CONTROL_BITS, byte);
+ pci_write_config8(dev, LPC_MISC_CONTROL_BITS, byte);
/*
* Enable hand-instance of the pulse generator and SPI
* controller prefetch of flash.
*/
- byte = pci_read_config8(SOC_SMBUS_DEV, LPC_HOST_CONTROL);
+ byte = pci_read_config8(dev, LPC_HOST_CONTROL);
byte |= PREFETCH_EN_SPI_FROM_HOST | T_START_ENH;
- pci_write_config8(SOC_SMBUS_DEV, LPC_HOST_CONTROL, byte);
+ pci_write_config8(dev, LPC_HOST_CONTROL, byte);
cmos_check_update_date();
@@ -161,9 +152,8 @@ static void lpc_set_resources(struct device *dev)
pci_dev_set_resources(dev);
}
-static void set_child_resource(struct device *child,
- u32 *reg,
- u32 *reg_x)
+static void set_child_resource(struct device *dev, struct device *child,
+ u32 *reg, u32 *reg_x)
{
struct resource *res;
u32 base, end;
@@ -272,7 +262,7 @@ static void set_child_resource(struct device *child,
wideio_index = sb_set_wideio_range(base, res->size);
if (wideio_index != WIDEIO_RANGE_ERROR) {
/* preserve wide IO related bits. */
- *reg_x = pci_read_config32(SOC_LPC_DEV,
+ *reg_x = pci_read_config32(dev,
LPC_IO_OR_MEM_DECODE_ENABLE);
printk(BIOS_DEBUG,
@@ -308,11 +298,8 @@ static void lpc_enable_childrens_resources(struct device *dev)
for (child = link->children; child;
child = child->sibling) {
if (child->enabled
- && (child->path.type == DEVICE_PATH_PNP)) {
- set_child_resource(child,
- &reg,
- &reg_x);
- }
+ && (child->path.type == DEVICE_PATH_PNP))
+ set_child_resource(dev, child, &reg, &reg_x);
}
}
pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, reg);