mb/intel/shadowmountain: Add bootblock and verstage code

This patch includes the bootblock and verstage changes for
shadowmountain board.

BUG=b:175808146
TEST= Build and boot shadowmountain board till early romstage.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I5f805baf42203306ff10e91a258d9117dd986c4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>

9 files changed, 282 insertions, 0 deletions

diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig
index a822bcc350..66ae63672e 100644
--- a/src/mainboard/intel/shadowmountain/Kconfig
+++ b/src/mainboard/intel/shadowmountain/Kconfig
@@ -3,9 +3,39 @@ if BOARD_INTEL_SHADOWMOUNTAIN
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_32768
+	select DRIVERS_I2C_GENERIC
+	select DRIVERS_I2C_HID
+	select DRIVERS_INTEL_DPTF
+	select DRIVERS_INTEL_PMC
+	select DRIVERS_SPI_ACPI
+	select DRIVERS_USB_ACPI
+	select EC_GOOGLE_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_BOARDID
+	select EC_GOOGLE_CHROMEEC_SKUID
+	select EC_GOOGLE_CHROMEEC_LPC
+	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_CHROMEOS
 	select SOC_INTEL_ALDERLAKE
 
+config CHROMEOS
+	select GBB_FLAG_FORCE_DEV_SWITCH_ON
+	select GBB_FLAG_FORCE_DEV_BOOT_USB
+	select GBB_FLAG_FORCE_DEV_BOOT_LEGACY
+	select GBB_FLAG_FORCE_MANUAL_RECOVERY
+	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
+
+config VBOOT
+	select EC_GOOGLE_CHROMEEC_SWITCHES
+	select VBOOT_LID_SWITCH
+	select VBOOT_MOCK_SECDATA
+	select HAS_RECOVERY_MRC_CACHE
+
+config DIMM_SPD_SIZE
+	int
+	default 512
+
 config DEVICETREE
 	string
 	default "variants/baseboard/devicetree.cb"
diff --git a/src/mainboard/intel/shadowmountain/Makefile.inc b/src/mainboard/intel/shadowmountain/Makefile.inc
new file mode 100644
index 0000000000..bc2be438d0
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/Makefile.inc
@@ -0,0 +1,13 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+bootblock-$(CONFIG_CHROMEOS) += chromeos.c
+
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+subdirs-y += variants/baseboard
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
diff --git a/src/mainboard/intel/shadowmountain/bootblock.c b/src/mainboard/intel/shadowmountain/bootblock.c
new file mode 100644
index 0000000000..98f58bc6a1
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/bootblock.c
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <bootblock_common.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	variant_configure_early_gpio_pads();
+}
diff --git a/src/mainboard/intel/shadowmountain/chromeos.c b/src/mainboard/intel/shadowmountain/chromeos.c
new file mode 100644
index 0000000000..35a54a8aca
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/chromeos.c
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boot/coreboot_tables.h>
+#include <gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	struct lb_gpio chromeos_gpios[] = {
+		{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+		{-1, ACTIVE_HIGH, 0, "power"},
+		{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+		{GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW),
+		 "EC in RW"},
+	};
+	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+int get_write_protect_state(void)
+{
+	/* Read PCH_WP GPIO. */
+	return gpio_get(GPIO_PCH_WP);
+}
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	const struct cros_gpio *gpios;
+	size_t num;
+
+	gpios = variant_cros_gpios(&num);
+	chromeos_acpi_gpio_generate(gpios, num);
+}
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/Makefile.inc b/src/mainboard/intel/shadowmountain/variants/baseboard/Makefile.inc
new file mode 100644
index 0000000000..a084537cb9
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/Makefile.inc
@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+bootblock-y += early_gpio.c
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
index fbd7d72f9f..1b3e37537b 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
@@ -1,5 +1,101 @@
 chip soc/intel/alderlake
+
 	device cpu_cluster 0 on
 		device lapic 0 on end
 	end
+
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	register "pmc_gpe0_dw0" = "GPP_C"
+	register "pmc_gpe0_dw1" = "GPP_D"
+	register "pmc_gpe0_dw2" = "GPP_E"
+
+	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+	register "gen1_dec" = "0x00fc0801"
+	register "gen2_dec" = "0x000c0201"
+	# EC memory map range is 0x900-0x9ff
+	register "gen3_dec" = "0x00fc0901"
+
+	device domain 0 on
+		device pci 00.0 on  end # Host Bridge
+		device pci 02.0 on  end # Graphics
+		device pci 04.0 on  end # DPTF
+		device pci 05.0 on  end # IPU
+		device pci 06.0 on  end # PEG60
+		device pci 07.0 on  end # TBT_PCIe0
+		device pci 07.1 on  end # TBT_PCIe1
+		device pci 07.2 on  end # TBT_PCIe2
+		device pci 07.3 on  end # TBT_PCIe3
+		device pci 08.0 off end # GNA
+		device pci 09.0 off end # NPK
+		device pci 0a.0 off end # Crash-log SRAM
+		device pci 0d.0 on  end # USB xHCI
+		device pci 0d.1 on  end # USB xDCI (OTG)
+		device pci 0d.2 on  end
+		device pci 0d.3 on  end # TBT DMA1
+		device pci 0e.0 off end # VMD
+		device pci 10.0 off end
+		device pci 10.1 off end
+		device pci 10.2 on  end # CNVi: BT
+		device pci 10.6 off end # THC0
+		device pci 10.7 off end # THC1
+		device pci 11.0 off end
+		device pci 11.1 off end
+		device pci 11.2 off end
+		device pci 11.3 off end
+		device pci 11.4 off end
+		device pci 11.5 off end
+		device pci 12.0 off end # SensorHUB
+		device pci 12.5 off end
+		device pci 12.6 off end # GSPI2
+		device pci 13.0 off end # GSPI3
+		device pci 13.1 off end
+		device pci 14.0 on  end # USB3.1 xHCI
+		device pci 14.1 off end # USB3.1 xDCI
+		device pci 14.2 off end # Shared RAM
+		device pci 14.3 on  end # CNVi: WiFi
+		device pci 15.0 on  end # I2C0
+		device pci 15.1 on  end # I2C1
+		device pci 15.2 on  end # I2C2
+		device pci 15.3 on  end # I2C3
+		device pci 16.0 off end # HECI1
+		device pci 16.1 off end # HECI2
+		device pci 16.2 off end # CSME
+		device pci 16.3 off end # CSME
+		device pci 16.4 off end # HECI3
+		device pci 16.5 off end # HECI4
+		device pci 17.0 on  end # SATA
+		device pci 19.0 off end # I2C4
+		device pci 19.1 on  end # I2C5
+		device pci 19.2 off end # UART2
+		device pci 1c.0 off end # RP1
+		device pci 1c.1 off end # RP2
+		device pci 1c.2 off end # RP3
+		device pci 1c.3 off end # RP4
+		device pci 1c.4 on  end # RP5
+		device pci 1c.5 off end # RP6
+		device pci 1c.6 off end # RP7
+		device pci 1c.7 on  end # RP8
+		device pci 1d.0 on  end # RP9
+		device pci 1d.1 off end # RP10
+		device pci 1d.2 off end # RP11
+		device pci 1d.3 off end # RP12
+		device pci 1e.0 on  end # UART0
+		device pci 1e.1 off end # UART1
+		device pci 1e.2 on  end # GSPI0
+		device pci 1e.3 off end # GSPI1
+		device pci 1f.0 on
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+			end
+		end # eSPI
+		device pci 1f.1 on  end # P2SB
+		device pci 1f.2 hidden  end # PMC
+		device pci 1f.3 on  end # Intel Audio SNDW
+		device pci 1f.4 on  end # SMBus
+		device pci 1f.5 on  end # SPI
+		device pci 1f.6 off end # GbE
+	end
 end
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c b/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c
new file mode 100644
index 0000000000..29e6184447
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+
+	/* UART0 RX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* UART0 TX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* A7 : MEM_STRAP_0 */
+	PAD_CFG_GPI(GPP_A7, NONE, DEEP),
+	/* A17 : MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_A17, NONE, DEEP),
+	/* A19 : MEM_STRAP_2 */
+	PAD_CFG_GPI(GPP_A19, NONE, DEEP),
+	/* A20 : MEM_STRAP_1 */
+	PAD_CFG_GPI(GPP_A20, NONE, DEEP),
+	/* B11 : PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
+
+	/* C0 : EN_PP3300_WLAN */
+	PAD_CFG_GPO(GPP_C0, 1, DEEP),
+	/* C3 : H1_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_C3, NONE, PLTRST, LEVEL, INVERT),
+
+	/* D10 : EN_PP3300_WWAN */
+	PAD_CFG_GPO(GPP_D10, 1, DEEP),
+
+	/* E10 : PCH_GSPI0_H1_TPM_CS_L */
+	PAD_CFG_NF(GPP_E10, NONE, DEEP, NF7),
+	/* E11 : PCH_GSPI0_H1_TPM_CLK */
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF7),
+	/* E12 : PCH_GSPIO_H1_TPM_MISO */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF7),
+	/* E13 : PCH_GSPI0_H1_TPM_MOSI_STRAP */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF7),
+
+	/* F14 : WLAN_PERST_L */
+	PAD_CFG_GPO(GPP_F14, 1, DEEP),
+	/* F20 : WWAN_RST_ODL
+	   To meet timing constraints - drive reset low.
+	   Deasserted in ramstage. */
+	PAD_CFG_GPO(GPP_F20, 0, DEEP),
+};
+
+void variant_configure_early_gpio_pads(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/gpio.h
new file mode 100644
index 0000000000..470a5d9e47
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/gpio.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_GPIO_H__
+#define __BASEBOARD_GPIO_H__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* EC in RW */
+#define GPIO_EC_IN_RW		GPP_A8
+
+/* BIOS Flash Write Protect */
+#define GPIO_PCH_WP		GPP_B11
+
+/* EC wake is LAN_WAKE# */
+#define GPE_EC_WAKE		GPE0_LAN_WAK
+
+/* EC sync IRQ */
+#define EC_SYNC_IRQ		GPP_C6_IRQ
+
+/* eSPI virtual wire reporting */
+#define EC_SCI_GPI		GPE0_ESPI
+
+#endif /* BASEBOARD_GPIO_H */
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h
new file mode 100644
index 0000000000..dbd0e67887
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_VARIANTS_H__
+#define __BASEBOARD_VARIANTS_H__
+
+#include <soc/gpio.h>
+#include <soc/meminit.h>
+#include <stddef.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/*
+ * The next set of functions return the gpio table and fill in the number of
+ * entries for each table.
+ */
+const struct cros_gpio *variant_cros_gpios(size_t *num);
+
+void variant_configure_early_gpio_pads(void);
+
+#endif /* __BASEBOARD_VARIANTS_H__ */