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authorKane Chen <kane.chen@intel.com>2014-08-01 10:59:20 -0700
committerMarc Jones <marc.jones@se-eng.com>2015-03-27 05:39:03 +0100
commit124f53fa9961bf70be719163ffb9a6bb85a9088c (patch)
tree51ee02d86b75dddaf1159f5cb040266f3dc799dd
parent84b9cf4756ff5cda10d4683c5957b6748c3ca377 (diff)
samus: Disable CMDPWR on broadwell
Workaround for auto shutdown issue on broadwell SKU. Now we can see C7 transition, and MRC fastboot BUG=chrome-os-partner:29787,chrome-os-partner:29117 BRANCH=None TEST=build ok and boot on samus Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Commit-Id: 932152b16c3943b00bd317e7370402dda451529f Original-Change-Id: Id1f174b67fa3e6f248dd8b21aee25e6e01abf33e Original-Reviewed-on: https://chromium-review.googlesource.com/210870 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Kane Chen <kane.chen@intel.com> Original-Commit-Queue: Kane Chen <kane.chen@intel.com> (cherry picked from commit 932152b16c3943b00bd317e7370402dda451529f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie9fb792635b39d33136cef576ae5559013d5947a Reviewed-on: http://review.coreboot.org/8950 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
-rw-r--r--src/mainboard/google/samus/romstage.c3
-rw-r--r--src/soc/intel/broadwell/broadwell/pei_data.h2
2 files changed, 3 insertions, 2 deletions
diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c
index b26cc4ece8..44d712e69e 100644
--- a/src/mainboard/google/samus/romstage.c
+++ b/src/mainboard/google/samus/romstage.c
@@ -59,8 +59,7 @@ void mainboard_romstage_entry(struct romstage_params *rp)
* Disable use of PEI saved data to work around memory issues.
*/
if (cpu_family_model() == BROADWELL_FAMILY_ULT) {
- pei_data.disable_self_refresh = 1;
- pei_data.disable_saved_data = 1;
+ pei_data.disable_cmd_pwr = 1;
}
/* Initalize memory */
diff --git a/src/soc/intel/broadwell/broadwell/pei_data.h b/src/soc/intel/broadwell/broadwell/pei_data.h
index 07b04d24d4..19b4451f89 100644
--- a/src/soc/intel/broadwell/broadwell/pei_data.h
+++ b/src/soc/intel/broadwell/broadwell/pei_data.h
@@ -124,6 +124,8 @@ struct pei_data
int max_ddr3_freq;
/* Disable self refresh */
int disable_self_refresh;
+ /* Disable cmd power/CKEPD */
+ int disable_cmd_pwr;
/* USB port configuration */
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS];