intel/lynxpoint,broadwell: Fix eDP display in Windows, SeaBios & Tiano

Without this patch, eDP output is non-functional pre-graphics driver
regardless of payload (SeaBIOS, Tianocore) or video init method
(VBIOS, GOP driver) and once the standard Windows Intel HD graphics
driver is loaded.

Test: Boot Windows on peppy and auron_paine, install Intel HD
Graphics driver, observe functional eDP output with full video
acceleration.

Debugging method: adjust location of call to run VBIOS within
coreboot, observed that eDP output functional if the VBIOS is run
before the power optimizer lines, broken if run afterwards.

Change-Id: I6d8252e3de396887c84533e355f41693b9ea7514
Signed-off-by: Prabal Saha <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/15261
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

4 files changed, 22 insertions, 0 deletions

diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 2d6176af6b..9be3b1dd1d 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -215,4 +215,13 @@ config CHIPSET_BOOTBLOCK_INCLUDE
 	string
 	default "soc/intel/broadwell/bootblock/timestamp.inc"
 
+config BROADWELL_POWER_OPTIMIZER
+	bool "Enable Power Optimizer"
+	default y if CHROMEOS
+	help
+		Enable the power optimizer for the High Speed I/O
+		Power Control (HSIOPC).  This can break graphics
+		under Windows, but can improve battery life under
+		'mostly idle' conditions.
+
 endif
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 7ec9b46708..40297d2006 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -260,6 +260,7 @@ static const struct reg_script pch_pm_init_script[] = {
 	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33b4, 0x00007001),
 	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3350, 0x022ddfff),
 	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3354, 0x00000001),
+#if IS_ENABLED(CONFIG_BROADWELL_POWER_OPTIMIZER)
 	/* Power Optimizer */
 	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x08000000),
 	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x08000080),
@@ -271,6 +272,7 @@ static const struct reg_script pch_pm_init_script[] = {
 	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a84, 0x00001005),
 	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x2fff2fb1),
 	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x00008000),
+#endif
 	REG_SCRIPT_END
 };
 
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index eea0c01043..7615e69cc3 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -96,4 +96,13 @@ config LOCK_MANAGEMENT_ENGINE
 	bool
 	default n
 
+config LYNXPOINT_POWER_OPTIMIZER
+	bool "Enable Power Optimizer"
+	default y if CHROMEOS
+	help
+		Enable the power optimizer for the High Speed I/O
+		Power Control (HSIOPC).  This can break graphics
+		under Windows, but can improve battery life under
+		'mostly idle' conditions.
+
 endif
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index f4c3826aa9..1d20bbbe3b 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -346,6 +346,7 @@ const struct rcba_config_instruction lpt_lp_pm_rcba[] = {
 	RCBA_RMW_REG_32(0x33b4,  0, 0x00007001),
 	RCBA_RMW_REG_32(0x3350,  0, 0x022ddfff),
 	RCBA_RMW_REG_32(0x3354,  0, 0x00000001),
+#if IS_ENABLED(CONFIG_LYNXPOINT_POWER_OPTIMIZER)
 	RCBA_RMW_REG_32(0x33d4, ~0, 0x08000000),  /* Power Optimizer */
 	RCBA_RMW_REG_32(0x33c8, ~0, 0x08000080),  /* Power Optimizer */
 	RCBA_RMW_REG_32(0x2b10,  0, 0x0000883c),  /* Power Optimizer */
@@ -353,6 +354,7 @@ const struct rcba_config_instruction lpt_lp_pm_rcba[] = {
 	RCBA_RMW_REG_32(0x2b24,  0, 0x40000005),  /* Power Optimizer */
 	RCBA_RMW_REG_32(0x2b20,  0, 0x0005db01),  /* Power Optimizer */
 	RCBA_RMW_REG_32(0x3a80,  0, 0x05145005),
+#endif
 	RCBA_END_CONFIG
 };