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authorMarshall Dawson <marshalldawson3rd@gmail.com>2017-11-08 15:43:06 -0700
committerAaron Durbin <adurbin@chromium.org>2017-11-10 19:17:42 +0000
commit0756880b804a3798561937220e471321c05d6c81 (patch)
tree699ec55b50c6960d16953d51b3688668123b8117
parentc5ada656200ecd4efcadf7ea5e33dfaea56d4ef7 (diff)
amd/stoneyridge: Add function to find Pm1EvtBlk base
The AcpiPm1EvtBlk base I/O address is configured in PMx60. Add a helper function to read this. The register is not lockable so it shouldn't be assumed to be at its original address. Change-Id: I91ebfb454c2d2ae561e658d903f33bfb34e1ad6f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/soc/amd/stoneyridge/include/soc/southbridge.h1
-rw-r--r--src/soc/amd/stoneyridge/sb_util.c5
2 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 3bc92967a3..771554a40e 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -265,6 +265,7 @@ void smi_write8(uint8_t offset, uint8_t value);
void smi_write16(uint8_t offset, uint16_t value);
void smi_write32(uint8_t offset, uint32_t value);
uint16_t pm_acpi_pm_cnt_blk(void);
+uint16_t pm_acpi_pm_evt_blk(void);
int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
int s3_save_nvram_early(u32 dword, int size, int nvram_pos);
void bootblock_fch_early_init(void);
diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c
index ebf791d6ff..f7c6b45ac3 100644
--- a/src/soc/amd/stoneyridge/sb_util.c
+++ b/src/soc/amd/stoneyridge/sb_util.c
@@ -79,3 +79,8 @@ uint16_t pm_acpi_pm_cnt_blk(void)
{
return pm_read16(PM1_CNT_BLK);
}
+
+uint16_t pm_acpi_pm_evt_blk(void)
+{
+ return pm_read16(PM_EVT_BLK);
+}