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authorAaron Durbin <adurbin@chromium.org>2015-07-13 14:03:41 -0500
committerPatrick Georgi <pgeorgi@google.com>2015-07-21 20:05:50 +0200
commit02b3243dd39291425c325a1e2df6618c5a45d934 (patch)
treefa63a97f28c19d7e2962b95f91e6c4aaaf1e6a33
parent356cabbe35dd2e1c05f9e76c6f079b08e1c97ed8 (diff)
skylake: honor pcie root port settings already in chip.h
For some unkonwn reason the pcie root port settings weren't being honored in the device tree. Fix that omission. BUG=chrome-os-partner:41861 BRANCH=None TEST=Built with CONFIG_DISPLAY_UPD_DATA and noted devicetree settings were being honored. Change-Id: Id880eca57544efb13f5cbbc06b2634c86b7c5d29 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2d00e68ce6cfcb3d63d69848f4a8ce232f6c1257 Original-Change-Id: Idd37d65374842294f4b0c91eb841c6d1d93e92ee Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285027 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/10987 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/soc/intel/skylake/romstage/romstage.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 6d1310a2ed..4230664911 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -90,6 +90,13 @@ void soc_memory_init_params(MEMORY_INIT_UPD *params)
for (i = 0; i < PchSerialIoIndexMax; i++)
params->SerialIoDevMode[i] = config->SerialIoDevMode[i];
+ memcpy(params->PcieRpEnable, config->PcieRpEnable,
+ sizeof(params->PcieRpEnable));
+ memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport,
+ sizeof(params->PcieRpClkReqSupport));
+ memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber,
+ sizeof(params->PcieRpClkReqNumber));
+
params->MmioSize = 0x800; /* 2GB in MB */
params->TsegSize = CONFIG_SMM_TSEG_SIZE;
params->IedSize = config->IedSize;