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authorSubrata Banik <subrata.banik@intel.com>2016-11-23 00:54:47 +0530
committerMartin Roth <martinroth@google.com>2016-11-30 16:54:36 +0100
commit0068dfdcc8c2a80508cdd44909d9a2561a30a0e5 (patch)
tree5ddb85a539c8d65c3535879b19dc7133c054a4ff /3rdparty
parenteedf6d8aa81e85b52d3c150dc992cbfb3077988d (diff)
soc/intel/skylake: Remove pad configuration size hardcoding
Existing GPIO driver inside coreboot use some hardcoded magic number to calculate gpio pad offset. Avoid this kind of hardcoding. Change-Id: I6110435574b141c57f366ccb1fbe9bf49d4dd70a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/17571 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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