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author | Subrata Banik <subrata.banik@intel.com> | 2019-11-01 18:12:58 +0530 |
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committer | Subrata Banik <subrata.banik@intel.com> | 2019-11-09 03:26:10 +0000 |
commit | 930c31c63ab2e2a2654090f4968217f2cd3125f3 (patch) | |
tree | df1949d80ea7dcbc5a3a71256d5cd57f6b384908 /3rdparty | |
parent | f307ffbe47f014bbea83a1da044e95210d66f56f (diff) |
soc/intel/tigerlake/bootblock: Do initial SoC commit till bootblock
Clone entirely from Icelake
List of changes on top off initial icelake clone
1. Replace "Icelake" with "Tigerlake"
2. Replace "icl" with "tgl"
3. Replace "icp" with "tgp"
4. Rename structure based on Icelake with Tigerlake
5. Add CPU/PCH/SA EDS document number and chapter number
6. Add required headers into include/soc/ from ICL directory
Tiger Lake specific changes will follow in subsequent patches.
1. Add Tigerlake specific device IDs (CPU/PCH/SA)
Change-Id: Id7a05f4b183028550d805f02a8078ab69862a62e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Diffstat (limited to '3rdparty')
0 files changed, 0 insertions, 0 deletions