imgtec/pistachio: DDR2, DDR3: DLL reset set

Bit 8 of the MR register is automatically set by the PHY
during memory initilization but having it set in the
register leads to a more clear understanding.

Tested on Pistachio bring up board; DDR2 and DDR3 are
initialized properly.

Change-Id: Ie6953e2a96ba2961521b372d280f362ee1c52b94
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12764
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

0 files changed, 0 insertions, 0 deletions