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authorSubrata Banik <subrata.banik@intel.com>2019-01-30 18:44:09 +0530
committerSubrata Banik <subrata.banik@intel.com>2019-02-01 04:30:59 +0000
commit3f559d960c637f09f74bbe217c562498ca1a5311 (patch)
tree02424e41908ede33a4e7c86d70fabd44071a4c3b /3rdparty
parentc6c4d00182fe5083a3be43a76aa7bba71f57b0bb (diff)
soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix
TEST=Dump SSDT entries to verify _CST between S0ix enable and disable. >> iasl -d SSDT # to generate SSDT.dsl Change-Id: I82d8bf9d143263a80a544f6e11186a3bc9c41052 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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