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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2018-08-22 14:43:24 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-08-23 15:52:39 +0000 |
| commit | 0e1a526242476ac9470f30bc0059d00cd499cacf (patch) | |
| tree | 59841fff123b15bdc5276c266aa391234a2878ed /3rdparty | |
| parent | 053851f283e8a9239cff8f667dba958fbc3ce63e (diff) | |
siemens/mc_apl1: Make adjustments for the 1st redesign of this mainboard
For the 1st redesign of mc_apl1 mainboard some adjustments are
necessary:
- The FPGA is now connected directly via a PCIe Root Port
- Internal Apollo Lake UARTs are now used
- Adjusting GPIO settings
Change-Id: I8917a52325306f24d1c39a88dac47b0cee760d57
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to '3rdparty')
0 files changed, 0 insertions, 0 deletions