diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2022-02-05 19:40:01 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-09 14:20:05 +0000 |
| commit | 9b5b17feca7d970879230e35941645abf7ff926c (patch) | |
| tree | 28b8b04a6fd117ce877ba94634e0cdfb9b8010f3 /3rdparty | |
| parent | 3922aa5c2ce56c4cd562ab906093b94c65172bd1 (diff) | |
soc/intel/alderlake: Define USB2_PORT_MAX_TYPE_C macro
The patch defines USB2_PORT_MAX_TYPE_C macro to allow mark the type_c
flag.The USB2_PORT_MAX_TYPE_C macro modifies the USB2 configuration to
indicate the port mapped to Type-C and sets Max TX and Pre-emp
settings. This is an extension to existing macro USB2_PORT_MAX.
The change is required to enable port reset event on a USB2 port.
This event is passed to USB3 upstream ports to upgrade back to super
speed (USB3) after a downgrade during low power state.
BUG=b:193287279
TEST=Build the code for Gimble board
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I464f139d8e367907191c04f9170ac53d327776ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61623
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to '3rdparty')
0 files changed, 0 insertions, 0 deletions