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authorRaul E Rangel <rrangel@chromium.org>2020-12-14 16:55:09 -0700
committerFelix Held <felix-coreboot@felixheld.de>2021-01-06 17:26:30 +0000
commit2f5fd1147442978264f062422812ec12f64a23a5 (patch)
treecbcfb771d8e9da6f7ceeb6fa58412c74629ead72 /3rdparty/vboot
parent9541d1792a38c4e500edb1de0570002355423808 (diff)
soc/amd/picasso: Fix ACPI PCI routing table
The original routing table did not handle all 8 INTx interrupts. Additionally it also didn't take the swizzling into account. Now that we know how AGESA programs the routing table we can correctly generate it. We still route the PCI interrupts through the FCH IOAPIC. A follow up will have the GNB IOAPIC handle the PCI interrupts. There is still work to be done to fix the legacy PCI_IRQ register for each PCI device. We can then remove the mainboard_pirq_data from each mainboard. BUG=b:170595019 TEST=Used ezkinil Boot kernel with `pci=nomsi amd_iommu=off noapic` and `pci=nomsi amd_iommu=off` then verified system was usable and verified /proc/interrupts looked correct. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I2b2cce9913081d5cd456043ba619a79c1dfd4a8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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