diff options
author | Casper Chang <casper_chang@wistron.corp-partner.google.com> | 2022-03-09 16:48:58 +0800 |
---|---|---|
committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-03-14 16:18:52 +0000 |
commit | f7abb4fccf076defbaa19a80e4d11582f3564330 (patch) | |
tree | 3d256fc1ff151cca34830255bdd492684d3e38a8 /3rdparty/intel-sec-tools | |
parent | 13f49ce754cf8c7d341432836a1e13e6cab1b71e (diff) |
mb/google/brya/var/primus{4es}: add eMMC enable pin in ramstage
Currently the BayHub eMMC enable pin is using the default
configuration from the baseboard, which leads to RTD3 not being able
to control the GPIO when exiting and entering suspend. To fix this,
program the GPIO in the ramstage GPIO table.
BUG=b:222436260
TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage
scope enable pin while performing suspend stress and enable pin
works as expected.
test suspend stress 1000 cycles passed on primus.
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I1b6f164cc326bd368addb1e143ad2cbd449bb08d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to '3rdparty/intel-sec-tools')
0 files changed, 0 insertions, 0 deletions