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author | Angel Pons <th3fanbus@gmail.com> | 2020-11-19 12:49:07 +0100 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-22 22:13:45 +0000 |
commit | 2a7d752aaa9f999059cf3b88956961ecc1540ba6 (patch) | |
tree | de38628b91f55aa07164a37649b03529e88b8565 /3rdparty/chromeec | |
parent | 9fbb1b096ff64e83a822d165fb732f22a2ec6e79 (diff) |
nb/intel/sandybridge: Rename and refactor `discover_timC_write`
This is actually aggressive write training, similar to aggressive read
training. Rename it accordingly and refactor it to improve clarity.
Enabling IOSAV_n_SPECIAL_COMMAND_ADDR optimizations must only be done
for later Ivy Bridge steppings. Therefore, guard the code accordingly.
Change-Id: Ia3331b95c265113d94cb5d66c57a97cb77fc3dc9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to '3rdparty/chromeec')
0 files changed, 0 insertions, 0 deletions