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author | Felix Held <felix-coreboot@felixheld.de> | 2023-04-29 01:59:31 +0200 |
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committer | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-05-03 16:15:45 +0000 |
commit | 026caf5def38df8cc2dca0e1acd7adc063e03951 (patch) | |
tree | 3f451922da47c23142656891fe162c99c6a3f3fa /.mailmap | |
parent | 662d7af70bc8e060921f57aaec328619382b4852 (diff) |
soc/amd/common/block/lpc/lpc: increase size of SPI BAR to 4kByte
The memory map granularity for those devices is 4kByte.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8806128bdce8988f5cd7c8fa8a342fdb01eb7f42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to '.mailmap')
0 files changed, 0 insertions, 0 deletions