soc/intel/tigerlake: Update FSP params for Jasper Lake

Update FSP parameters for various configurations like:
- graphics
- USB
- PCIe root ports
- SD card
- eMMC
- Audio
- Basic UART configuration

These are the initial settings for JSL.

This patch also corrects the debug_interface_flag definitions.

TEST=Build dedede board

Change-Id: Ia8e88f92989fe40d7bd1c28947e005cc0d862fcb
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>

0 files changed, 0 insertions, 0 deletions