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| author | Chris.Wang <chris.wang@amd.corp-partner.google.com> | 2023-03-16 15:11:36 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-29 13:20:25 +0000 |
| commit | f83b282856ebf83194fd7e2bd7adb5e65a2bd384 (patch) | |
| tree | b0b92b8d371ff3df1a2f562a4558cb5a6e8585a2 /.gitreview | |
| parent | 8f2953b279d6cb1b73c791412818e144e253175b (diff) | |
soc/amd/mendocino: Add FSP parameter for eDP power sequence adjustment
Add UPD parameter for eDP power sequence adjust.
The pwr_on_vary_bl_to_blon is set one unit per 4ms.
BUG=b:271704149
TEST=Build; Verify the UPD was pass to system integrated table;
measure the power on sequence on whiterun
Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I25c9f962e70f599c780259f0943a03f8aa7cbfd1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Diffstat (limited to '.gitreview')
0 files changed, 0 insertions, 0 deletions