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authorHannah Williams <hannah.williams@intel.com>2016-06-02 15:00:36 -0700
committerMartin Roth <martinroth@google.com>2016-07-07 17:02:57 +0200
commit7124882aeb45ed863c12dcd9cea2f3ab033b2ee4 (patch)
treec97e672517cdfce859e40101429cd41a66ce1b1b /.gitreview
parente1d6aa6e4195f5fce6cb65d39d36289e6786fa36 (diff)
board/intel/amenia: Enable LPSS S0ix
This setting will enable S0ix for LPSS Change-Id: Ie07cb8437d0cee61a03638aa980fd3322fef0c4e Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15056 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
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