mb/google/hatch: Add SoC and EC asl files in DSDT

This implementation adds below code:

1. Add SOC ACPI code in dsdt.asl
   -> platform.asl
   -> globalnvs.asl
   -> cpu.asl
   -> northbridge.asl
   -> southbridge.asl
   -> sleepstate.asl

2. Add chromeos.asl in dsdt.asl

3. Add EC ACPI code in dsdt.asl
   -> superio.asl
   -> ec.asl

4. Remove config for WAK/PTS ACPI method as chromeec
   doesn't implement those.

BUG=b:120914069
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot

Change-Id: Icf1b1d7e34a7e863139c3583903f3b1e2cdc8da6
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

0 files changed, 0 insertions, 0 deletions