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| author | Vaibhav Shankar <vaibhav.shankar@intel.com> | 2017-10-16 10:16:27 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-18 20:07:45 +0000 |
| commit | f36ed21c573d62583ca2a86eed594acd149e0c4c (patch) | |
| tree | a9c0f2a618b8343f6250a4fb217f6e8031120893 /.gitreview | |
| parent | f46a9a0d3ad3157de3e354b4314fe9c5c3b69dd2 (diff) | |
mainboard/intel/cannonlake_rvp: Enable hardware P state control
This patch provides configuration parameter to enable/disable
Intel Speed Shift Technology.
Change-Id: I95a240e8be6e19ac0e14698ab33543c491a8c974
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/22049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to '.gitreview')
0 files changed, 0 insertions, 0 deletions