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authorMaximilian Brune <maximilian.brune@9elements.com>2022-10-24 20:31:18 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-11-04 15:17:20 +0000
commit2c984883ecf0cb2342e855f15ae8c874c0c033dc (patch)
treebe34d3e3927aa8a1b5d294278324ae1c7c1e459d /.gitmodules
parentffc79fbe2733de0d5ede4c4debd7de580ec6c1e8 (diff)
soc/intel/alderlake: Add IBECC
Add In Band Error Correction Code to Alderlake SOC's. It's currently needed and tested for the Prodrive Atlas mainboard. After enabling it in the UPD, FSP-M takes care of enabling IBECC. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I9cc2ed6defa1223aa422b9b0d8145f8f8b3dd12e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68756 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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