arch/x86/acpi: Add support for writing ACPI DBG2 table

Add a function to create an ACPI DBG2 table, which is a Microsoft
ACPI extension for providing a description of the available debug
interface on a board.

A convenience function is provided for creating a DBG2 table with
a 16550 UART based on a PCI device.

This is tested by generating a device and verifying it with iasl:

[000h 0000   4]                    Signature : "DBG2"
[004h 0004   4]                 Table Length : 00000061
[008h 0008   1]                     Revision : 00
[009h 0009   1]                     Checksum : 3B
[00Ah 0010   6]                       Oem ID : "CORE  "
[010h 0016   8]                 Oem Table ID : "COREBOOT"
[018h 0024   4]                 Oem Revision : 00000000
[01Ch 0028   4]              Asl Compiler ID : "CORE"
[020h 0032   4]        Asl Compiler Revision : 00000000

[024h 0036   4]                  Info Offset : 0000002C
[028h 0040   4]                   Info Count : 00000001

[02Ch 0044   1]                     Revision : 00
[02Dh 0045   2]                       Length : 0035
[02Fh 0047   1]               Register Count : 01
[030h 0048   2]              Namepath Length : 000F
[032h 0050   2]              Namepath Offset : 0026
[034h 0052   2]              OEM Data Length : 0000
[036h 0054   2]              OEM Data Offset : 0000
[038h 0056   2]                    Port Type : 8000
[03Ah 0058   2]                 Port Subtype : 0000
[03Ch 0060   2]                     Reserved : 0000
[03Eh 0062   2]          Base Address Offset : 0016
[040h 0064   2]          Address Size Offset : 0022

[042h 0066  12]        Base Address Register : [Generic Address Structure]
[042h 0066   1]                     Space ID : 00 [SystemMemory]
[043h 0067   1]                    Bit Width : 00
[044h 0068   1]                   Bit Offset : 00
[045h 0069   1]         Encoded Access Width : 03 [DWord Access:32]
[046h 0070   8]                      Address : 00000000FE034000

[04Eh 0078   4]                 Address Size : 00001000

[052h 0082  15]                     Namepath : "\_SB.PCI0.UAR2"

Raw Table Data: Length 97 (0x61)

  0000: 44 42 47 32 61 00 00 00 00 3B 43 4F 52 45 20 20  // DBG2a....;CORE
  0010: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45  // COREBOOT....CORE
  0020: 00 00 00 00 2C 00 00 00 01 00 00 00 00 35 00 01  // ....,........5..
  0030: 0F 00 26 00 00 00 00 00 00 80 00 00 00 00 16 00  // ..&.............
  0040: 22 00 00 00 00 03 00 40 03 FE 00 00 00 00 00 10  // "......@........
  0050: 00 00 5C 5F 53 42 2E 50 43 49 30 2E 55 41 52 32  // ..\_SB.PCI0.UAR2
  0060: 00                                               // .

Change-Id: I55aa3f24776b2f8aa38d7da117f422d8b8ec5479
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/22452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

0 files changed, 0 insertions, 0 deletions