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author | Felix Held <felix-coreboot@felixheld.de> | 2019-12-28 18:44:06 +0100 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2019-12-29 12:19:43 +0000 |
commit | bc3668a4687f68fb1bfb39ec89fa863879fed2ac (patch) | |
tree | 00ef4ed278d6217dc16f01408289b2677458984d /.gitmodules | |
parent | 4902fee4412eb15bee5f5e164302730de0ce195e (diff) |
nb/intel/sandybridge: add and use defines for ME base and mask registers
Timeless build results in identical image for X230.
Change-Id: Ia2bd26b97cb2ae77f29d8978f62d2f6be12b43e1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to '.gitmodules')
0 files changed, 0 insertions, 0 deletions