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| author | John Zhao <john.zhao@intel.com> | 2020-05-13 15:40:07 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-18 07:34:08 +0000 |
| commit | 7a05e6e2ad75dc1e28a50f3f309d8e7aecaf2526 (patch) | |
| tree | 419240764873aca2adff99689a764b1cec84c39c /.gitmodules | |
| parent | d7b9e363e3ec09eb5e2977d16085fdb3cd1334ce (diff) | |
soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1En
This adds FSP UPD TcssDma0En and TcssDma1En for configuration.
BUG=:b:146624360
TEST=Built and booted on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I04af970f74ab9dfe84f9c0c09ec2098e0093fa57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to '.gitmodules')
0 files changed, 0 insertions, 0 deletions